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| REJ09B0015-0200Z 32 32171 Group User's Manual RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 2.00 Revision date: Sep 19, 2003 www.renesas.com Keep safety first in your circuit designs! * Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials * These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. * Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). * When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. * Please contact Renesas Technology Corporation for further details on these materials or t he products contained therein. REVISION HISTORY Rev. 0.1 1.0 Date Page Apr 8, 2000 Nov 1, 2002 all all P1-6 32171 Group User's Manual Description Summary - First edition issued Explanation of the M32171F2 added Designation of M32R/E changed to M32R/ECU Description in Section 1.1.6, Built-in Full-CAN Function, corrected Incorrect: Compliant with CAN Specification V2.0B Correct: Compliant with CAN Specification V2.0B active P1-7 P1-8 P1-10 P1-11 M32171F2 added to the internal flash memory in Figure 1.2.1 M32171F2 added to the internal flash memory in Table 1.2.2 Table 1.2.4, List of Type Name added Note 1 in Figure 1.3.1 corrected Incorrect: Operates with a 5 V power supply Correct: Operates with a 3.3 V or 5 V power supply P1-12 Functional description of pin names VCCE and OSC-VCC in Table 1.3.1corrected Explanation of WR added to the functional description of clock in Table 1.3.1 P1-13 P1-17 P3-5 P3-6 Explanation of the A-D converter in Table 1.3.1 corrected Figure 1.4.1 corrected Figure 3.1.3, "M32171F2 address space," added Table 3.2.1 corrected Note 1 in Table 3.2.1 corrected P3-7 P3-8 P4-25 P5-13 P5-17 P5-19 P6-2 Figure 3.2.3 "M32171F2 operation mode and internal ROM/external extended areas," added M32171F2 added to Table 3.3.1 Section 4.13, "Precautions on EIT," added Relevant names of causes added to Table 5.4.1 Relevant names of causes added to Table 5.5.1 Explanation added to (4) "Enabling multiple interrupts" in Section 5.5.2, "Processing of Internal Peripheral I/O Interrupts by Handler" Description in Section 6.1, "Outline of the Internal Memory," corrected Precautions added to Table 6.2.1 P6-3 P6-5 P6-7 P6-8 P6-13 P6-22 P6-25 M32171F2 added to Table 6.3.1 Precautions added Precautions (Note 2) added Precautions added Figure 6.4.4, "FCNT4 Register Usage Example 2," added Table 6.5.1 corrected Precautions (Note 2, 3, 4) added to Table 6.5.2 (1/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P6-27 P6-30 P6-38 P6-40 P6-43 P6-46 32171 Group User's Manual Description Summary Table 6.5.5, "M32171F2's relevant block and specificaion address," added Table 6.5.9, "Block configuration of M32171F2 flash memory," added Figure 6.5.15, Figure 6.5.16 and Figure 6.5.17 corrected (3) M32171F2 added to Section 6.5.4, "Flash Programming Time (Reference Value)" Precautios (Notes 2, 3, 4) added Figure 6.7.6, "Virtual-flash emulation area of the M32171F2 divided in 8 Kbyte units," added Figure 6.7.7, "Virtual-flash emulation area of the M32171F2 divided in 4 Kbyte units," added P6-47, P6-48 P6-49 Incorrect register names in Figures 6.7.8 through 6.7.11 corrected Incorrect: LBAKNKAD Correct: LBANKAD Figure 6.7.12, "Virtual-flash bank register setup values for the M32171F2 when divided in 8 Kbyte units," added Figure 6.7.13, "Virtual-flash bank register setup values for the M32171F2 when divided in 4 Kbyte units," added P6-55 P6-56 P7-3 P7-4 to P7-7 P8-4 Section 6.9, "Internal Flash Memory Protect Functions," added Explanation in Section 6.10, "Precautions to Be Taken when Reprogramming Flash Memory," changed Table 7.3.1 corrected Tables 7.3.2 to 7.3.5, " Pin Status When Reset," added or corrected Table 8.2.1 corrected Precautions in Table 8.2.1 corrected P8-22 to P8-25 P8-26 P9-4 P10-1 to P10-142 P10-4 P10-5 P10-12 P10-31 P10-47 P10-55 P10-66 Figures 8.4.1 to 8.4.4 corrected Section 8.5, "Precautions on Input/output Ports," added Figure 9.1.2, "Causes of DMAC Requests Connection Diagram," added Chapter 10 overall, designation of the prescaler unified to PRS Port numbers added to Figure 10.1.1 Port numbers added to Figure 10.1.2 Port numbers added to Figure 10.2.2 Figure 10.2.5 changed Port numbers added to Figure 10.3.1 Port number added to Figure 10.3.5 Figure 10.3.8 corrected (2/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P10-84 P10-93 P10-96 P10-124 P10-130 P10-133 P10-141 P11-3 32171 Group User's Manual Description Summary Port numbers added to Figure 10.4.1 Port numbers added to Figure 10.4.5 Port numbers added to Figure 10.4.6 Port numbers added to Figure 10.5.1 Figure 10.5.3 corrected Port numbers added to Figure 10.6.1 Note 1 in Figure 10.6.3 corrected Table 11.1.1 corrected Precautions in Table 11.1.1 corrected P11-4 P11-35 Register names in Figure 11.1.1 corrected Method for calculating the conversion time during A-D conversion mode and that for conversion time during comparate mode explained separately Table 11.3.1 and precausions corrected Figure 11.3.4, "Conceptual Diagram of Conversion Time in Comparate Mode," added Table 11.3.2, "Conversion Clock Cycles in Comparate Mode," added P11-37 to P11-38 P11-40 P12-12 P12-24 Explanation in Section 11.3.5, "Definition of the A-D Conversion Accuracy," changed A section "Regarding the analog input pins" added to Section 11.4, "Precautions on Using Figure 12.2.4 corrected Description of the last line in Section 12.2.8, "SIO Baud Rate Register," corrected Incorrect: 7 or less Correct: greater than 7 to P11-42 A-D Converters" P12-58 Figure 12.7.5, "Detecting the Start Bit, added Figure 12.7.6, "Example of an Invalid Start Bit (Not Received)," added Figure 12.7.7, "Delay when Receiving," added P13-2 Description in Section 13.1, "Outline of the CAN Module," corrected Incorrect: Compliant with CAN (Controller Area Network) Specification V2.0B Correct: Compliant with CAN (Controller Area Network) Specification V2.0B active Protocol explanation in Table 13.1.1 corrected Incorrect: CAN Specification V2.0B Correct: CAN Specification V2.0B active Explanation of acceptance filters in Table 13.1.1 changed Precautions in Table 13.1.1 changed P13-3 P13-19 P13-20 Figure 13.1.1 corrected Table 13.2.2, "Example for Setting Bit Timing when CPU Clock: 32 MHz," added Note 3 added (3/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P13-28 P13-29 P13-30 P13-35 Figure 13.2.5 corrected Figure 13.2.6 corrected Figure 13.2.7 corrected 32171 Group User's Manual Description Summary Figure 13.2.8, "Relationship between Mask Registers and the Controlled Slots," added Figure 13.2.9, " Operation of the Acceptance Filter," added P13-61 P13-64 P13-65 P13-68 P13-71 P13-75 P13-78 P13-82 P15-6 P15-12 P16-6 P18-2 P19-7 P19-14 P19-14 P19-15 P19-16 Explanation in (2) Confirming that transmission is idle corrected Figure 13.5.2 corrected Explanation in (2) Confirming that reception is idle corrected Figure 13.6.2 corrected Explanation in (2) Confirming that transmission is idle corrected Figure 13.7.2 corrected Explanation in (2) Confirming that reception is idle corrected Figure 13.8.2 corrected Figures 15.2.1 to 15.2.6 corrected (Address signals A12 to A30 and chip select signals Figures 15.3.1 and 15.3.2 corrected (Address signals A12 to A30 and chip select signals Figures 16.3.1 to 16.3.14 corrected (Address signals A12 to A30 and chip select signals Precautions added to Figure 18.1.1 Figure 19.4.2 corrected Precautions added to Section 19.5, "Boundary Scan Description Language" BSDL description language for the 32171 (Figures 19.5.1 to 19.5.14) deleted Precautions added to Figure 19.6.1 Precautions added to Section 19.7, "Processing Pins when Not Using JTAG" Figure 19.7.1, "Processing Pins when Not Using JTAG," added to P15-11 CS0, CS1 separately shown) to P15-13 CS0, CS1 separately shown) to P16-19 CS0, CS1 separately shown) P20-1 In Chapter 20, explanation of power supply turn-on/turn-off sequences during Chapter 20 overall, designations of "5V system" and "3.3V system" changed to "external I/O" and "internal," respectively to P20-16 VCCE=3.3V added P20-12 P20-13 P20-15 P21-3, P21-4 P21-5 Figure 20.3.6 corrected Figure 20.3.8, "CPU Reset State" deleted Figure 20.3.12, "SRAM Data Backup State" deleted Recommended operating conditions corrected (minimum value of analog reference voltage added) (1) Electrical characteristics when f(XIN) = 10 MHz corrected (4/8) REVISION HISTORY Rev. 1.0 Date Page Nov 1, 2002 P21-7 P21-10 P21-11 to P21-18 P21-19 P21-22 P21-32 32171 Group User's Manual Description Summary (3) Electrical characteristics when f(XIN) = 8 MHz corrected Section 21.1.4, "A/D Conversion Characteristics," corrected Section 21.2, "Electrical Characteristics (when VCCE = 3.3V)," added Explanation in Section 21.3.1, "Timing Requirements," corrected (9) Table of rated RTD timings corrected Figure 21.3.12 corrected Appendix 3 Appendix 3, "Processing Unused Pins," added Appendix 4 Appendix 4, "Summary of Precautions," added "Precautions about Noise" in Appendix 3 moved to Appendix 4, "Summary of Precautions" 2.00 Sep 19, 2003 all P1-4 P2-14 P3-8 The word "Mitsubishi" deleted or replaced by "Renesas" Figure 1.1.1 and Table 1.1.1 newly added Section 2.7, "Precautions on CPU" added Addresses in the third line of Section 3.3 corrected Incorrect: Correct: H'0000 0000 to H'0003 FFFF H'0000 0000 to H'003F FFFF H'0080 4000 through H'0080 3FFF H'0080 4000 through H'0080 7FFF P3-9 Addresses in Section 3.4.1 corrected Incorrect: Correct: P4-20 Designation in (2), "Updating SM, IE and C bits" in the Section [EIT processing] corrected Incorrect: Correct: SM SM 0 Unchanged P5-end Section 5.2 and 5.3 placed in reversed Title of Section 5.3 (former 5.2) changed Before: After: Interrupt Sources of Internal Peripheral Interrupt Request Sources in Internal Peripheral total of 31 total of 22 P5-2 Description in the fourth line of Section 5.1 corrected Incorrect: Correct: Note added to Table 5.1.1 P5-3 P5-5, P5-6 P5-7 P5-9 P5-10 Description in Section 5.2.3 altered Description in (1), "IREQ (Interrupt Request) bit (D3 or D11)", altered Figures 5.2.2, "Configuration of the Interrupt Control Register (Edge-recognized Type)", and 5.2.3, "Configuration of the Interrupt Control Register (Level-recognized Type)", changed Figure 5.1.1 altered Note (former CAUTION) altered (5/8) REVISION HISTORY Rev. Date Page 2.00 Sep 19, 2003 P5-17 P5-19, P5-20 P5-21 P6-43 P6-44 P6-50 P7-1 to P7-7 P7-3 P10-end P10-19, P10-20 P10-49 P10-72 P10-82 P10-122 P10-87 P10-96 P10-103 P10-115 P10-119 P10-124 Table 5.5.1 corrected 32171 Group User's Manual Description Summary Description in (2) to (4), Section 5.5.2 changed Figure 5.5.2 changed Note 3 for Section 6.7.1 corrected Notes in Figures 6.7.2 and 6.7.3 corrected Figure, "Virtual-Flash Emulation Mode to Normal Mode Return Sequence" deleted Chapter 7 overall, The phrase "reset release" changed to " exiting reset" Registers R0-R15 added to Table 7.3.1 Sections 10.7 to 10.9 deleted Note added Figure 10.3.2, "Count Clock Dependent Delay", newly added Figure (former 10.3.13), "Prescaler Delay", deleted Figure 10.3.22 deleted Description of DMA transfer request generation (for only the TIO8) newly added Description of "Count clock-dependent delay" along with Figure 10.4.2 newly added Figure 10.4.7, "Outline Diagram of TIO5-9 Clock/Enable Inputs", altered Description of W= corrected P10-83 to Section 10.4 overall, (3), "Precautions on using TIO PWM output mode", newly added Last item of Section 10.4.13. (2) added Figure 10.5.1 corrected Description of "Count clock-dependent delay" along with Figure 10.5.2 newly added P10-141 P11-6 P11-16 P11-36 Second paragraph of Section 10.6.7. (1) corrected Description added to Section 11.1.2 Note 1 added Conversion time for Comparator mode in Table 11.3.3 corrected Incorrect: Correct: 27 29 P11-39 P11-41, P11-42 "AD1CSTP" is deleted from the explanation of "Forcible termination during scan operation" in Section 11.14 Equations altered (6/8) REVISION HISTORY Rev. Date Page 2.00 Sep 19, 2003 P12-3 32171 Group User's Manual Description Summary Baud rate for UART mode in Table 12.1.1 changed Before: 156K bits/sec After: 1.25M bits/sec Note in Section 12.2.3. (1) corrected Last paragraph of Section 12.2.8 changed Figure 12.4.1 corrected Note deleted Figure 12.6.3 corrected Note deleted P12-14 P12-24 P12-34 P12-42 P12-46 P12-53 Figure 12.7.1 corrected Note deleted P12-60 P13-9 P13-77 P15-16 P17-4 P17-6 P18-5 P19-13 P19-14 P21-5, P21-7 P21-9 P21-11 P21-18 Description in "Setting of Baud Rate (BRG) Regiser" partly deleted Notes and Explanation added for 13.2.1. (4), "RFST (Forcible Reset) bit" Figure 13.7.3 altered Figure 5.4.3 corrected Note 4 for Figure 17.2.3 corrected Note 2 for Figure 17.3.2 altered Figure 18.2.1 altered TAP states for (2) continuous access to the same datagister in Figure 19.4.5 corrected Note in Section 19.5 altered Note 3 changed Figures of ICCI-3V temperature characteristics newly added Descriptions of IIAN in the tables, Section 21.1.4 addedd (2) Electrical characteristics of each power supply pin when f(XIN)=10 MHz corrected to (4) Electrical characteristics of each power supply pin when f(XIN)= 8 MHz "A-D conversion characteristics (Referenced to AVCC=VREF=VCCE=3.3V, Ta=25C, f(XIN) = 8.0 MHz Unless Otherwise Noted)" corrected to "A-D conversion characteristics (Referenced to AVCC=VREF=VCCE=3.3V, Ta = -40 to 85C, f(XIN) = 8.0 MHz Unless Otherwise Noted)" Descriptions of IIAN in the tables, Section 21.2.4 added P21-19 P21-23 P21-25 P21-26 P21-27 P22-2 Maximum rated value for td(RTDCLKH-RTDRXD) corrected "tv(BCLKL-BHWL)" corrected to "td(BCLKL-D)" Parameter, "Byte enable delay time after write" corrected to "Valid Byte enable timer after write" Figure 21.3.1 altered Normal mode added to (1) Test conditions (7/8) REVISION HISTORY Rev. Date Page 3-2, 3-3 4-11 Note 3 altered 32171 Group User's Manual Description Summary 2.00 Sep 19, 2003 Appendix Processing for Input/output ports in Table A3.1.1 alterd Appendix Last item of Appendix 4.8.6 added Appendix Last line of the 1st paragraph deleted 4-24 Appendix Description in (2), "Wiring of clock input/output pins", altered 4-25 4-26 Figure A4.13.2 changed newly added Figure A4.13.7, "Exmple Wiring of the MOD0 and MOD1 Pins", altered Appendix Description in (1), "Avoidance from large-current signal lines", altered 4-29 Figure A4.13.7, "Example Wiring of Large-current Signal Lines", changed Appendix (3), "Wiring of the VCNT pin", and Figure A4.13.3, "Example Wiring of the VCNT Pin", Appendix Figure A.4.13.8, "Example Wiring of Rapidly Level-changing Signal Lines", changed 4-30 Appendix (3), "Protection against signal lines that are the source of strong noise", and Figures 4-31,32 A4.13.9, "Example Processing of a Noise-laden Pin", and A4.13.10, "Example Processing of Pins Adjacent to the Oscillator and VCNT Pins", newly added (8/8) How to read internal I/O register tables Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. State of Register at Reset: Represents the initial state of each register immediately after reset with hexadecimal numbers (undefined bits after reset are indicated each in column .) At read: ... read enabled ? ... read disabled (read value invalid) 0 ... Read always as 0 1 ... Read always as 1 : Write enabled : Write enable conditionally (include some conditions at write) : Write disabled (Written value invalid) { At write: - Not implemented in the shaded portion. 1 D0 1 Abit 2 Bbit 3 Cbit Registers represented with thick rectangles are accessible only with halfwords or words (not accessible with bytes). 4 2 D 0 1 Bit name Not assigned. Abit (...................) 2 Bbit (...................) 3 Cbit (...................) 0: ----1: ----0: ----1: ----0: ----1: ----Function 3 4 Table of contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32171 .......................................................................................... 1-2 1.1.1 M32R Family CPU Core .................................................................. 1-2 1.1.2 Built-in Multiply-Accumulate Operation Function ............................. 1-3 1.1.3 Built-in Flash Memory and RAM ...................................................... 1-3 1.1.4 Built-in Clock Frequency Multiplier .................................................. 1-4 1.1.5 Built-in Powerful Peripheral Functions ............................................. 1-4 1.1.6 Built-in Full-CAN Function ............................................................... 1-6 1.1.7 Built-in Debug Function ................................................................... 1-6 1.2 Block Diagram ................................................................................................... 1-7 1.3 Pin Function .................................................................................................... 1-11 1.4 Pin Layout ........................................................................................................ 1-17 CHAPTER 2 CPU 2.1 CPU Registers ................................................................................................... 2-2 2.2 General-purpose Registers .............................................................................. 2-2 2.3 Control Registers .............................................................................................. 2-3 2.3.1 Processor Status Word Register: PSW (CR0) ................................. 2-4 2.3.2 Condition Bit Register: CBR (CR1) .................................................. 2-5 2.3.3 Interrupt Stack Pointer: SPI (CR2) ................................................... 2-5 User Stack Pointer: SPU (CR3) 2.3.4 Backup PC: BPC (CR6) ................................................................... 2-5 2.4 Accumulator ...................................................................................................... 2-6 2.5 Program Counter .............................................................................................. 2-6 2.6 Data Formats ..................................................................................................... 2-7 2.6.1 Data Types ...................................................................................... 2-7 2.6.2 Data Formats ................................................................................... 2-8 2.7 Precautions on CPU ....................................................................................... 2-14 (1) CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space ................................................................................ 3-2 3.2 Operation Modes ............................................................................................... 3-6 3.3 Internal ROM Area and External Extension Area ........................................... 3-8 3.3.1 Internal ROM Area ........................................................................... 3-8 3.3.2 External Extension Area ................................................................. 3-8 3.4 Internal RAM Area and SFR Area .................................................................... 3-9 3.4.1 Internal RAM Area ........................................................................... 3-9 3.4.2 Special Function Register (SFR) Area ............................................. 3-9 3.5 EIT Vector Entry .............................................................................................. 3-23 3.6 ICU Vector Table ............................................................................................. 3-24 3.7 Notes on Address Space ................................................................................ 3-26 CHAPTER 4 EIT 4.1 Outline of EIT ..................................................................................................... 4-2 4.2 EIT Events .......................................................................................................... 4-3 4.2.1 Exception ......................................................................................... 4-3 4.2.2 Interrupt ........................................................................................... 4-3 4.2.3 Trap ................................................................................................. 4-3 4.3 EIT Processing Procedure ............................................................................... 4-4 4.4 EIT Processing Mechanism ............................................................................. 4-6 4.5 Acceptance of EIT Events ................................................................................ 4-7 4.6 Saving and Restoring the PC and PSW .......................................................... 4-8 4.7 EIT Vector Entry .............................................................................................. 4-10 4.8 Exception Processing .................................................................................... 4-11 4.8.1 Reserved Instruction Exception (RIE) ............................................ 4-11 4.8.2 Address Exception (AE) ................................................................. 4-13 4.9 Interrupt Processing ....................................................................................... 4-15 4.9.1 Reset Interrupt (RI) ........................................................................ 4-15 4.9.2 System Break Interrupt (SBI) ......................................................... 4-16 4.9.3 External Interrupt (EI) .................................................................... 4-18 (2) 4.10 Trap Processing ............................................................................................ 4-20 4.10.1 Trap (TRAP) ................................................................................ 4-20 4.11 EIT Priority Levels ......................................................................................... 4-22 4.12 Example of EIT Processing .......................................................................... 4-23 4.13 Precautions on EIT ....................................................................................... 4-25 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) ......................................................... 5-2 5.2 ICU Related Registers ...................................................................................... 5-4 5.2.1 Interrupt Vector Register .................................................................. 5-5 5.2.2 Interrupt Mask Register ................................................................... 5-6 5.2.3 SBI (System Break Interrupt) Control Register ................................ 5-7 5.2.4 Interrupt Control Registers ............................................................... 5-8 5.3 Interrupt Sources in Internal Peripheral I/O ................................................. 5-12 5.4 ICU Vector Table ............................................................................................. 5-13 5.5 Description of Interrupt Operation ................................................................ 5-16 5.5.1 Acceptance of Internal Peripheral I/O Interrupts ............................ 5-16 5.5.2 Processing of Internal Peripheral I/O Interrupts by Handlers ........ 5-19 5.6 Description of System Break Interrupt (SBI) Operation .............................. 5-22 5.6.1 Acceptance of SBI ......................................................................... 5-22 5.6.2 SBI Processing by Handler ............................................................ 5-22 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory ........................................................................ 6-2 6.2 Internal RAM ...................................................................................................... 6-2 6.3 Internal Flash Memory ...................................................................................... 6-3 6.4 Registers Associated with the Internal Flash Memory .................................. 6-3 6.4.1 Flash Mode Register ........................................................................ 6-4 6.4.2 Flash Status Registers ..................................................................... 6-5 6.4.3 Flash Control Registers ................................................................... 6-8 6.4.4 Virtual Flash L Bank Register ........................................................ 6-14 6.4.5 Virtual Flash S Bank Registers ...................................................... 6-15 (3) 6.5 Programming of the Internal Flash Memory ................................................. 6-16 6.5.1 Outline of Programming Flash Memory ......................................... 6-16 6.5.2 Controlling Operation Mode during Programming Flash ............... 6-22 6.5.3 Programming Procedure to the Internal Flash Memory ................. 6-25 6.5.4 Flash Program Time (for Reference) ............................................. 6-39 6.6 Boot ROM ........................................................................................................ 6-41 6.7 Virtual Flash Emulation Function .................................................................. 6-42 6.7.1 Virtual Flash Emulation Area ......................................................... 6-43 6.7.2 Entering Virtual Flash Emulation Mode ......................................... 6-50 6.7.3 Application Example of Virtual Flash Emulation Mode .................. 6-51 6.8 Connecting to A Serial Programmer ............................................................. 6-53 6.9 Internal Flash Memory Protect Functions .................................................... 6-55 6.10 Precautions to Be Taken When Reprogramming Flash Memory ............. 6-56 CHAPTER 7 RESET 7.1 Outline of Reset ................................................................................................ 7-2 7.2 Reset Operation ................................................................................................ 7-2 7.2.1 Reset at Power-on ........................................................................... 7-2 7.2.2 Reset during Operation .................................................................... 7-2 7.2.3 Reset Vector Relocation during Flash Reprogramming .................. 7-2 7.3 Internal State after Exiting Reset ..................................................................... 7-3 7.4 Things To Be Considered after Exiting Reset ................................................ 7-8 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports .......................................................................... 8-2 8.2 Selecting Pin Functions ................................................................................... 8-4 8.3 Input/Output Port Related Registers ............................................................... 8-6 8.3.1 Port Data Registers ......................................................................... 8-8 8.3.2 Port Direction Registers ................................................................... 8-9 8.3.3 Port Operation Mode Registers ..................................................... 8-10 8.4 Port Peripheral Circuits .................................................................................. 8-22 8.5 Precautions on Input/output Ports ................................................................ 8-26 (4) CHAPTER 9 DMAC 9.1 Outline of the DMAC ......................................................................................... 9-2 9.2 DMAC Related Registers .................................................................................. 9-5 9.2.1 DMA Channel Control Register ....................................................... 9-7 9.2.2 DMA Software Request Generation Registers .............................. 9-18 9.2.3 DMA Source Address Registers .................................................... 9-19 9.2.4 DMA Destination Address Registers ............................................. 9-20 9.2.5 DMA Transfer Count Registers ...................................................... 9-21 9.2.6 DMA Interrupt Request Status Registers ....................................... 9-22 9.2.7 DMA Interrupt Mask Registers ....................................................... 9-24 9.3 Functional Description of the DMAC ............................................................ 9-28 9.3.1 Cause of DMA Request ................................................................. 9-28 9.3.2 DMA Transfer Processing Procedure ............................................ 9-32 9.3.3 Starting DMA ................................................................................. 9-33 9.3.4 Channel Priority ............................................................................. 9-33 9.3.5 Gaining and Releasing Control of the Internal Bus ........................ 9-33 9.3.6 Transfer Units ................................................................................ 9-34 9.3.7 Transfer Counts ............................................................................. 9-34 9.3.8 Address Space .............................................................................. 9-34 9.3.9 Transfer Operation ......................................................................... 9-34 9.3.10 End of DMA and Interrupt ............................................................ 9-38 9.3.11 Status of Each Register after Completion of DMA Transfer ........ 9-38 9.4 Precautions about the DMAC ........................................................................ 9-39 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers ................................................................... 10-2 10.2 Common Units of Multijunction Timer ........................................................ 10-7 10.2.1 Timer Common Register Map ...................................................... 10-7 10.2.2 Prescaler Unit .............................................................................. 10-9 10.2.3 Clock Bus/Input-Output Event Bus Control Unit ........................ 10-10 10.2.4 Input Processing Control Unit .................................................... 10-15 10.2.5 Output Flip-Flop Control Unit ..................................................... 10-21 10.2.6 Interrupt Control Unit ................................................................. 10-29 (5) 10.3 TOP (Output-related 16-bit Timer) ............................................................. 10-46 10.3.1 Outline of TOP ........................................................................... 10-46 10.3.2 Outline of Each Mode of TOP .................................................... 10-48 10.3.3 TOP Related Register Map ........................................................ 10-50 10.3.4 TOP Control Registers ............................................................... 10-53 10.3.5 TOP Counters (TOP0CT-TOP10CT) ......................................... 10-60 10.3.6 TOP Reload Registers (TOP0RL-TOP10RL) ............................ 10-61 10.3.7 TOP Correction Registers (TOP0CC-TOP10CC) ..................... 10-62 10.3.8 TOP Enable Control Register .................................................... 10-63 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) ......... 10-67 10.3.10 Operation in TOP Delayed Single-shot Output Mode (With Correction Function) ...... 10-74 10.3.11 Operation in TOP Continuous Output Mode (Without Correction Function) .............. 10-79 10.4 TIO (Input/Output-related 16-bit Timer) ..................................................... 10-83 10.4.1 Outline of TIO ............................................................................ 10-83 10.4.2 Outline of Each Mode of TIO ..................................................... 10-85 10.4.3 TIO Related Register Map ......................................................... 10-88 10.4.4 TIO Control Registers ................................................................ 10-91 10.4.5 TIO Counter (TIO0CT-TIO9CT) ............................................... 10-102 10.4.6 TIO Reload 0/ Measure Register (TIO0RL0-TIO9RL0) ........... 10-103 10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1) ......................... 10-104 10.4.8 TIO Enable Control Registers .................................................. 10-105 10.4.9 Operation in TIO Measure Free-run/Clear Input Modes .......... 10-108 10.4.10 Operation in TIO Noise Processing Input Mode ..................... 10-112 10.4.11 Operation in TIO PWM Output Mode ...................................... 10-113 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) .. 10-117 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) .. 10-119 10.4.14 Operation in TIO Continuous Output Mode (Without Correction Function) 10-121 10.5 TMS (Input-related 16-bit Timer) .............................................................. 10-123 10.5.1 Outline of TMS ......................................................................... 10-123 10.5.2 Outline of TMS Operation ........................................................ 10-123 10.5.3 TMS Related Register Map ..................................................... 10-125 10.5.4 TMS Control Registers ............................................................ 10-126 10.5.5 TMS Counter (TMS0CT, TMS1CT) ......................................... 10-128 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) ............ 10-129 10.5.7 Operation of TMS Measure Input ............................................ 10-130 (6) 10.6 TML (Input-related 32-bit Timer) .............................................................. 10-132 10.6.1 Outline of TML ......................................................................... 10-132 10.6.2 Outline of TML Operation ........................................................ 10-133 10.6.3 TML Related Register Map ...................................................... 10-134 10.6.4 TML Control Registers ............................................................. 10-135 10.6.5 TML Counters .......................................................................... 10-137 10.6.6 TML Measure Registers .......................................................... 10-139 10.6.7 Operation of TML Measure Input ............................................. 10-141 CHAPTER 11 A-D CONVERTER 11.1 Outline of A-D Converter .............................................................................. 11-2 11.1.1 Conversion Modes ....................................................................... 11-5 11.1.2 Operation Modes ......................................................................... 11-6 11.1.3 Special Operation Modes .......................................................... 11-10 11.1.4 A-D Converter Interrupt and DMA Transfer Requests ............... 11-13 11.2 A-D Converter Related Registers .............................................................. 11-14 11.2.1 A-D Single Mode Register 0 ...................................................... 11-16 11.2.2 A-D Single Mode Register 1 ...................................................... 11-19 11.2.3 A-D Scan Mode Register 0 ........................................................ 11-21 11.2.4 A-D Scan Mode Register 1 ........................................................ 11-24 11.2.5 A-D Successive Approximation Register ................................... 11-26 11.2.6 A-D0 Comparate Data Register .................................................. 11-27 11.2.7 10-bit A-D Data Registers .......................................................... 11-28 11.2.8 8-bit A-D Data Registers ............................................................ 11-29 11.3 Functional Description of A-D Converter ................................................. 11-30 11.3.1 How to Find Along Input Voltages ............................................. 11-30 11.3.2 A-D Conversion by Successive Approximation Method ............ 11-31 11.3.3 Comparator Operation ............................................................... 11-33 11.3.4 Calculation of the A-D Conversion Time .................................... 11-34 11.3.5 Definition of the A-D Conversion Accuracy ................................ 11-37 11.4 Precautions on Using A-D Converter ........................................................ 11-39 CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O ....................................................................................... 12-2 (7) 12.2 Serial I/O Related Registers ......................................................................... 12-6 12.2.1 SIO Interrupt Related Registers ................................................... 12-7 12.2.2 SIO Interrupt Control Registers ................................................... 12-9 12.2.3 SIO Transmit Control Registers ................................................. 12-13 12.2.4 SIO Transmit/Receive Mode Registers ..................................... 12-15 12.2.5 SIO Transmit Buffer Registers ................................................... 12-18 12.2.6 SIO Receive Buffer Registers .................................................... 12-19 12.2.7 SIO Receive Control Registers .................................................. 12-20 12.2.8 SIO Baud Rate Registers .......................................................... 12-23 12.3 Transmit Operation in CSIO Mode ............................................................ 12-25 12.3.1 Setting the CSIO Baud Rate ...................................................... 12-25 12.3.2 Initial Settings for CSIO Transmission ....................................... 12-26 12.3.3 Starting CSIO Transmission ...................................................... 12-28 12.3.4 Successive CSIO Transmission ................................................ 12-28 12.3.5 Processing at End of CSIO Transmission ................................. 12-29 12.3.6 Transmit Interrupt ...................................................................... 12-29 12.3.7 Transmit DMA Transfer Request ............................................... 12-29 12.3.8 Typical CSIO Transmit Operation .............................................. 12-31 12.4 Receive Operation in CSIO Mode .............................................................. 12-33 12.4.1 Initial Settings for CSIO Reception ............................................ 12-33 12.4.2 Starting CSIO Reception ........................................................... 12-35 12.4.3 Processing at End of CSIO Reception ....................................... 12-35 12.4.4 About Successive Reception ..................................................... 12-36 12.4.5 Flags Indicating the Status of CSIO Receive Operation ............ 12-37 12.4.6 Typical CSIO Receive Operation ............................................... 12-38 12.5 Precautions on Using CSIO Mode ............................................................. 12-40 12.6 Transmit Operation in UART Mode ........................................................... 12-42 12.6.1 Setting the UART Baud Rate ..................................................... 12-42 12.6.2 UART Transmit/Receive Data Formats ..................................... 12-43 12.6.3 Initial Settings for UART Transmission ...................................... 12-45 12.6.4 Starting UART Transmission ..................................................... 12-47 12.6.5 Successive UART Transmission ............................................... 12-47 12.6.6 Processing at End of UART Transmission ................................ 12-48 12.6.7 Transmit Interrupt ...................................................................... 12-48 12.6.8 Transmit DMA Transfer Request ............................................... 12-48 (8) 12.6.9 Typical UART Transmit Operation ............................................. 12-50 12.7 Receive Operation in UART Mode ............................................................. 12-52 12.7.1 Initial Settings for UART Reception ........................................... 12-52 12.7.2 Starting UART Reception .......................................................... 12-54 12.7.3 Processing at End of UART Reception ...................................... 12-54 12.7.4 Typical UART Receive Operation .............................................. 12-56 12.7.5 Detecting the Start Bit during UART Reception ......................... 12-58 12.8 Fixed Period Clock Output Function ......................................................... 12-59 12.9 Precautions on Using UART Mode ............................................................ 12-60 CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module .......................................................................... 13-2 13.2 CAN Module Related Registers ................................................................... 13-4 13.2.1 CAN Control Register .................................................................. 13-8 13.2.2 CAN Status Register .................................................................. 13-11 13.2.3 CAN Extended ID Register ........................................................ 13-15 13.2.4 CAN Configuration Register ...................................................... 13-16 13.2.5 CAN Time Stamp Count Register .............................................. 13-20 13.2.6 CAN Error Count Registers ....................................................... 13-21 13.2.7 CAN Baud Rate Prescaler ......................................................... 13-22 13.2.8 CAN Interrupt Related Registers ............................................... 13-23 13.2.9 CAN Mask Registers ................................................................. 13-31 13.2.10 CAN Message Slot Control Registers ...................................... 13-36 13.2.11 CAN Message Slots ................................................................. 13-40 13.3 CAN Protocol ............................................................................................... 13-55 13.3.1 CAN Protocol Frame .................................................................. 13-55 13.4 Initializing the CAN Module ........................................................................ 13-58 13.4.1 Initialization of the CAN Module ................................................. 13-58 13.5 Transmitting Data Frames .......................................................................... 13-61 13.5.1 Data Frame Transmit Procedure ............................................... 13-61 13.5.2 Data Frame Transmit Operation ................................................ 13-63 13.5.3 Transmit Abort Function ............................................................ 13-64 (9) 13.6 Receiving Data Frames .............................................................................. 13-65 13.6.1 Data Frame Receive Procedure ................................................ 13-65 13.6.2 Data Frame Receive Operation ................................................. 13-67 13.6.3 Reading Out Received Data Frames ......................................... 13-69 13.7 Transmitting Remote Frames .................................................................... 13-71 13.7.1 Remote Frame Transmit Procedure .......................................... 13-71 13.7.2 Remote Frame Transmit Operation ........................................... 13-73 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ...... 13-76 13.8 Receiving Remote Frames ......................................................................... 13-78 13.8.1 Remote Frame Receive Procedure ........................................... 13-78 13.8.2 Remote Frame Receive Operation ............................................ 13-80 CHAPTER 14 REAL-TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) .................................................. 14-2 14.2 Pin Function of the RTD ............................................................................... 14-3 14.3 Functional Description of the RTD .............................................................. 14-4 14.3.1 Outline of RTD Operation ............................................................ 14-4 14.3.2 Operation of RDR (Real-time RAM Content Output) ................... 14-5 14.3.3 Operation of WRR (RAM Content Forcible Rewrite) ................... 14-7 14.3.4 Operation of VER (Continuous Monitor) ...................................... 14-9 14.3.5 Operation of VEI (Interrupt Request) ......................................... 14-10 14.3.6 Operation of RCV (Recover from Runaway) ............................. 14-11 14.3.7 Method to Set a Specified Address when Using the RTD ......... 14-12 14.3.8 Resetting the RTD ..................................................................... 14-13 14.4 Typical Connection with the Host ............................................................. 14-14 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 External Bus Interface Related Signals ...................................................... 15-2 15.2 Read/Write Operations ................................................................................. 15-6 15.3 Bus Arbitration ............................................................................................ 15-12 15.4 Typical Connection of External Extension Memory ................................ 15-14 (10) CHAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller ...................................................................... 16-2 16.2 Wait Controller Related Registers ............................................................... 16-4 16.2.1 Wait Cycles Control Register (WTCCR) ...................................... 16-5 16.3 Typical Operation of the Wait Controller .................................................... 16-6 CHAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode ...................................................................... 17-2 17.2 Example of RAM Backup when Power is Down ......................................... 17-2 17.2.1 Normal Operating State ............................................................... 17-3 17.2.2 RAM Backup State ...................................................................... 17-4 17.3 Example of RAM Backup for Saving Power Consumption ....................... 17-5 17.3.1 Normal Operating State ............................................................... 17-6 17.3.2 RAM Backup State ...................................................................... 17-7 17.3.3 Precautions to Be Observed at Power-on ................................... 17-8 17.4 Exiting RAM Backup Mode (Wakeup) ......................................................... 17-9 CHAPTER 18 OSCILLATION CIRCUIT 18.1 Oscillator Circuit ........................................................................................... 18-2 18.1.1 Example of an Oscillator Circuit ................................................... 18-2 18.1.2 System Clock Output Function .................................................... 18-3 18.1.3 Oscillation Stabilization Time at Power-on .................................. 18-4 18.2 Clock Generator Circuit ................................................................................ 18-5 CHAPTER 19 JTAG 19.1 Outline of JTAG ............................................................................................. 19-2 19.2 Configuration of the JTAG Circuit ............................................................... 19-3 19.3 JTAG Registers ............................................................................................. 19-4 19.3.1 Instruction Register (JTAGIR) ...................................................... 19-4 19.3.2 Data Registers ............................................................................. 19-5 (11) 19.4 Basic Operation of JTAG ............................................................................. 19-6 19.4.1 Outline of JTAG Operation .......................................................... 19-6 19.4.2 IR Path Sequence ........................................................................ 19-8 19.4.3 DR Path Sequence .................................................................... 19-10 19.4.4 Examining and Setting Data Registers ...................................... 19-12 19.5 Boundary Scan Description Language ..................................................... 19-14 19.6 Precautions on Board Design when Using JTAG .................................... 19-15 19.7 Processing Pins when Not Using JTAG ................................................... 19-16 CHAPTER 20 POWER-ON/POWER-OFF SEQUENCE 20.1 Configuration of the Power Supply Circuit ................................................ 20-2 20.2 Power-On Sequence ..................................................................................... 20-4 20.2.1 Power-On Sequence When Not Using RAM Backup .................. 20-4 20.2.2 Power-On Sequence When Using RAM Backup ......................... 20-6 20.3 Power-off Sequence ..................................................................................... 20-8 20.3.1 Power-off Sequence When Not Using RAM Backup ................... 20-8 20.3.2 Power-off Sequence When Using RAM Backup ........................ 20-10 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Electrical Characteristics (VCCE = 5 V) ...................................................... 21-2 21.1.1 Absolute Maximum Ratings ......................................................... 21-2 21.1.2 Recommended Operating Conditions .......................................... 21-3 21.1.3 DC Characteristics ....................................................................... 21-5 21.1.4 A-D Conversion Characteristics ................................................. 21-11 21.2 Electrical Characteristics (VCCE = 3.3 V) ................................................. 21-12 21.2.1 Absolute Maximum Ratings ....................................................... 21-12 21.2.2 Recommended Operating Conditions ........................................ 21-13 21.2.3 DC Characteristics ..................................................................... 21-15 21.2.4 A-D Conversion Characteristics ................................................. 21-19 21.3 AC Characteristics ...................................................................................... 21-20 21.3.1 Timing Requirements ................................................................. 21-20 21.3.2 Switching Characteristics ........................................................... 21-24 21.3.3 AC Characteristics ..................................................................... 21-27 (12) CHAPTER 22 TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics .................................................................. 22-2 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing ....................................... Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/ECU Instruction Processing Time ..................... Appendix 2-2 APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example for Processing Unused Pins ......................... Appendix 3-2 APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Precautions Regarding the CPU .................................. Appendix 4-2 Appendix 4.1.1 Things to be noted for data transfer ................. Appendix 4-2 Appendix 4.2 Precautions on Address Space .................................... Appendix 4-2 Appendix 4.2.1 Virtual flash emulation function ........................ Appendix 4-2 Appendix 4.3 Precautions on EIT ........................................................ Appendix 4-3 Appendix 4.4 Precautions to Be Taken When Reprogramming Flash Memory ................................................................ Appendix 4-3 Appendix 4.5 Things to Be Considered after Exiting Reset ............. Appendix 4-4 Appendix 4.5.1 Input/output Ports ............................................ Appendix 4-4 Appendix 4.6 Precautions on Input/output Ports ............................... Appendix 4-4 Appendix 4.6.1 When using the ports in output mode .............. Appendix 4-4 Appendix 4.7 Precautions about the DMAC ........................................ Appendix 4-5 Appendix 4.7.1 About writing to DMAC related registers .......... Appendix 4-5 Appendix 4.7.2 Manipulating DMAC related registers by DMA transfer .................................................... Appendix 4-6 Appendix 4.7.3 About the DMA Intrrupt Reqest Status Register ........................................................... Appendix 4-6 (13) Appendix 4.7.4 About the stable operation of DMA transfer ..... Appendix 4-6 Appendix 4.8 Precautions on Multijunction Timers .......................... Appendix 4-7 Appendix 4.8.1 Precautions to be observed when using TOP single-shot output mode .......................... Appendix 4-7 Appendix 4.8.2 Precautions to be observed when using TOP delayed single-shot output mode ............ Appendix 4-9 Appendix 4.8.3 Precautions to be observed when using TOP continuous output mode ....................... Appendix 4-10 Appendix 4.8.4 Precautions to be observed when using TIO measure free-run/clear input modes ...... Appendix 4-11 Appendix 4.8.5 Precautions to be observed when using TIO single-shot output mode ......................... Appendix 4-11 Appendix 4.8.6 Precautions to be observed when using TIO delayed single-shot output mode ........... Appendix 4-11 Appendix 4.8.7 Precautions to be observed when using TIO continuous output mode ......................... Appendix 4-12 Appendix 4.8.8 Precautions to be observed when using TMS measure input ....................................... Appendix 4-12 Appendix 4.8.9 Precautions to be observed when using TML measure input ....................................... Appendix 4-13 Appendix 4.9 Precautions on Using A-D Converters ...................... Appendix 4-14 Appendix 4.10 Precautions on Serial I/O .......................................... Appendix 4-18 Appendix 4.10.1 Precautions on Using CSIO mode ............... Appendix 4-18 Appendix 4.10.2 Precautions on Using UART mode .............. Appendix 4-20 Appendix 4.11 Precautions on RAM Backup Mode ......................... Appendix 4-21 Appendix 4.11.1 Precautions to be observed at Power-on ..... Appendix 4-21 Appendix 4.12 Precautions on Processing JTAG Pins ................... Appendix 4-22 Appendix 4.12.1 Precautions on Board Design when Using JTAG ................................................. Appendix 4-22 Appendix 4.12.2 Processing Pins when Not Using JTAG ...... Appendix 4-23 Appendix 4.13 Precautions about Noise .......................................... Appendix 4-24 Appendix 4.13.1 Reduction of Wiring Length ......................... Appendix 4-24 Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines .................................... Appendix 4-27 (14) Appendix 4.13.3 Processing Analog Input Pin Wiring ............ Appendix 4-28 Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ............................................. Appendix 4-29 Appendix 4.13.5 Processing Input/Output Ports ..................... Appendix 4-33 (15) CHAPTER 1 OVERVIEW 1.1 1.2 1.3 1.4 Outline of the 32171 Block Diagram Pin Function Pin Layout 1 1.1 Outline of the 32171 1.1.1 M32R Family CPU Core (1) Based on RISC architecture OVERVIEW 1.1 Outline of the 32171 * The 32171 is a 32-bit RISC single-chip microcomputer which is built around the M32R family CPU core (hereafter referred to as the M32R) and incorporates flash memory, RAM, and various other peripheral functions-all integrated into a single chip. * The M32R is based on RISC architecture. Memory access is performed using load and store instructions, and various arithmetic operations are executed using register-to-register operation instructions. The M32R internally contains sixteen 32-bit general-purpose registers and has 83 distinct instructions. * The M32R supports compound instructions such as Load & Address Update and Store & Address Update, in addition to ordinary load and store instructions. These compound instructions help to speed up data transfers. (2) 5-stage pipelined processing * The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch, Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or register-to-register operation instructions, compound instructions such as Load & Address Update and Store & Address Update also are executed in one cycle. * Instructions are entered into the execution stage in the order they are fetched, but this does not always mean that the first instruction entered is executed first. If the execution of a load or store instruction entered earlier is delayed by one or more wait cycles inserted in memory access, a register-to-register operation instruction entered later may be executed before said load or store instruction. By using "out-of-order-completion" like this, the M32R controls instruction execution without wasting clock cycles. (3) Compact instruction code * The M32R instructions come in two types: one consisting of 16 bits in length, and the other consisting of 32 bits in length. Use of the 16-bit length instruction format especially helps to suppress the program code size. * Some 32-bit long instructions can branch directly to a location 32 Mbytes forward or backward from the instruction address being executed. Compared to architectures where address space is segmented, this direct jump allows for easy programming. 1-2 32171 Group User's Manual (Rev.2.00) 1 1.1.2 Built-in Multiply-Accumulate Operation Function (1) Built-in high-speed multiplier OVERVIEW 1.1 Outline of the 32171 * The M32R incorporates a 32-bit x 16-bit high-speed multiplier which enables it to execute a 32-bit x 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40 MHz internal CPU clock). (2) Supports Multiply-Accumulate operation instructions comparable to DSP * The M32R supports the following four modes of Multiply-Accumulate operation instructions (or multiplication instructions) using a 56-bit accumulator. Any of these operations can be executed in one cycle. (a) 16 high-order register bits x 16 high-order register bits (b) 16 low-order register bits x 16 low-order register bits (c) Entire 32 register bits x 16 high-order register bits (d) Entire 32 register bits x 16 low-order register bits * The M32R has instructions to round off the value stored in the accumulator to 16 or 32 bits, as well as instructions to shift the accumulator value to adjust digits and store the digit-adjusted value in a register. These instructions also can be executed in one cycle, so that when combined with high-speed data transfer instructions such as Load & Address Update and Store & Address Update, they enable the M32R to exhibit high data processing capability comparable to that of DSP. 1.1.3 Built-in Flash Memory and RAM * The 32171 contains flash memory and RAM which can be accessed with no wait states, allowing you to build a high-speed embedded system. * The internal flash memory allows for on-board programming (you can write to it while being mounted on the printed circuit board). Use of flash memory means the chip engineered at the development phase can be used directly in mass-production, so that you can smoothly migrate from prototype to mass-production without changing the printed circuit board. * The internal flash memory can be rewritten 100 times. * The internal flash memory has a virtual-flash emulation function, allowing the internal RAM to be artificially mapped into part of the internal flash memory. This function, when combined with the internal Real-Time Debugger (RTD), facilitates data tuning on ROM tables. * The internal RAM can be accessed for read or rewrite from an external device independently of the M32R by using RTD (real-time debugger). It is communicated with external devices by RTD's exclusive clock-synchronized serial I/O. 1-3 32171 Group User's Manual (Rev.2.00) 1 1.1.4 Built-in Clock Frequency Multiplier OVERVIEW 1.1 Outline of the 32171 * The 32171 internally multiplies the input clock signal frequency by 4 and the internal peripheral clock by 2. If the input clock frequency is 10.0 MHz, the CPU clock frequency will be 40 MHz and the internal clock frequency 20 MHz. XIN (8MHz - 10MHz) X4 CPUCLK (CPU clock) (32MHz - 40MHz) 1/2 BCLK (peripheral clock) (16MHz - 20MHz) 1/2 peripheral clock (8MHz - 10MHz) 1/4 Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.1 Clock Functional Block CPUCLK Features * CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R core, internal flah memory and inernal RAM. BCLK * Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. Clock output (BCLK pin output) 1/2 peripheral clock * A clock with the same frequency as f(BCLK) is output from this pin. * Count-source clock of MJT. Sampling clock of TCLK, TIN. 1.1.5 Built-in Powerful Peripheral Functions (1) Built-in multijunction timer (MJT) * The multijunction timer is configured with the following 37 channels timers: (a) (b) (c) (d) 16-bit output-related timer x 11 channels 16-bit input/output-related timer x 10 channels 16-bit input-related timer x 8 channels 32-bit input-related timer x 8 channels Each timer has multiple modes of operation, which can be selected according of the purpose of use. * The multijunction timer has internal clock bus, input event bus, and output event bus, allowing multiple timers to be combined for use internally. This provides a flexible way to make use of timer functions. * The output-related timers (TOP) have a correction function. This function allows the timer's count value in progress to be increased or reduced as desired, thus materializing real-time output control. 1-4 32171 Group User's Manual (Rev.2.00) 1 (2) Built-in 10-channel DMA OVERVIEW 1.1 Outline of the 32171 * The 10-channel DMA is built-in, supporting data transfers between internal peripheral I/Os or between internal peripheral I/O and internal RAM. Not only can DMA transfer requests be generated in software, but can also be triggered by a signal generated by an internal peripheral I/O (e.g., A-D converter, MJT, or serial I/O). * Cascaded connection between DMA channels (DMA transfer in a channel is started by completion of transfer in another) is also supported, allowing for high-speed transfer processing without imposing any extra load on the CPU. (3) Built-in 16-channel A-D converter * The 32171 contains one 16-channel A-D converter which can convert data in 10-bit resolution. In addition to single A-D conversion in each channel, successive A-D conversion in four, eight, or 16 channels combined into one unit is possible. * In addition to ordinary A-D conversion, a comparator mode is supported in which the A-D conversion result is compared with a given set value to determine the relative magnitudes of two quantities. * When A-D conversion is completed, the 32171 can generate not only an interrupt, but can also generate a DMA transfer request. * The 32171 supports two readout modes, so that A-D conversion results can be read out in 8 bits or 10 bits. (4) High-speed serial I/O * The 32171 incorporates 3 channels of serial I/O, which can be set for clock-synchronized serial I/O or UART. * When set for clock-synchronized serial I/O, the data transfer rate is a high 2 Mbits per second. * When data reception is completed or the transmit buffer becomes empty, the serial I/O can generate a DMA transfer request signal. (5) Built-in Real-Time Debugger (RTD) * The Real-Time Debugger (RTD) provides a function for the M32R/ECU's internal RAM to be accessed directly from an external device. The debugger communicates with external devices through its exclusive clock-synchronized serial I/O. * By using the RTD, you can read the contents of the internal RAM or rewrite its data from an external device independently of the M32R. * The debugger can generate an RTD interrupt to notify that RTD-based data transmission or reception is completed. 1-5 32171 Group User's Manual (Rev.2.00) 1 (6) Eight-level interrupt controller OVERVIEW 1.1 Outline of the 32171 * The interrupt controller manages interrupt requests from each internal peripheral I/O by resolving interrupt priority in eight levels including an interrupt-disabled state. Also, it can accept external interrupt requests due to power-down detection or generated by a watchdog timer as a System Break Interrupt (SBI). (7) Three operation modes * The M32R/ECU has three operation modes: single-chip mode, external extension mode, and processor mode. The address space and external pin functions of the M32R/ECU are switched over according to a mode in which it operates. The MOD0 and MOD1 pins are used to set a mode. (8) Wait controller * The wait controller supports access to external devices by the M32R. In all but single-chip mode, the external extension area provides 4 Mbytes of space. 1.1.6 Built-in Full-CAN Function * The 32171 contains CAN Specification V2.0B active-compliant CAN module, thereby providing 16 message slots. 1.1.7 Built-in Debug Function * The 32171 supports JTAG interface. Boundary scan test can be performed using this JTAG interface. 1-6 32171 Group User's Manual (Rev.2.00) 1 1.2 Block Diagram OVERVIEW 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32171. Features of each block are shown in Tables 1.2.1 through 1.2.3. 32171 M32R CPU core (max 40 MHz) Multiplieraccumulator (32 X 16 + 56) Internal bus interface DMA C (10 channels) Internal 32-bit bus Multijunction timer (MJT: 37 channels) Internal flash memory (M32171F4:512KB) (M32171F3:384KB) (M32171F2:256KB) A-D converter (10-bit resolution, 16 channels) Internal 16-bit bus Serial I/O (3 channels) Interrupt controller (22 sources, 8 levels) Internal RAM (16KB) Wait controller Full CAN (1 channel) Real-time debugger ( RTD) External bus interface PLL clock generator circuit Data Address Input/output port (JTAG), 97 lines Figure 1.2.1 Block Diagram of the 32171 1-7 32171 Group User's Manual (Rev.2.00) 1 Table 1.2.1 Features of the M32R Family CPU Core Functional Block M32R family CPU core Features * Bus specifications OVERVIEW 1.2 Block Diagram Basic bus cycle: 25 ns (when operating with 40 MHz CPU clock) Logical address space: 4Gbytes, linear External extension area: Maximum 4 Mbytes External data bus: 16 bits * Implementation: Five-stage pipeline * Internal 32-bit architecture for the core * Register configuration General-purpose register: 32 bits x 16 registers Control register: 32 bits x 5 registers * Instruction set 16-bit and 32-bit instruction formats 83 distinct instructions and 6 addressing modes * Built-in multiplier/accumulator (32 x 16 + 56) Table 1.2.2 Features of Internal Memory Functional Block RAM Features * Capacity : 16 Kbytes * No-wait access * By using RTD (real-time debugger), the internal RAM can be accessed for read or rewrite from external devices independently of the M32R. Flash memory * Capacity M32171F4 : 512 Kbytes M32171F3 : 384 Kbytes M32171F2 : 256 Kbytes * No-wait access * Durability: Can be rewritten 100 times 1-8 32171 Group User's Manual (Rev.2.00) 1 Table 1.2.3 Features of Internal Peripheral I/O Functional Block DMA Features * 10-channel DMA OVERVIEW 1.2 Block Diagram * Supports transfer between internal peripheral I/Os, between internal RAMs, and between internal peripheral I/O and internal RAM. * Capable of advanced DMA transfer when operating in combination with internal peripheral I/O * Capable of cascaded connection between DMA channels (DMA transfer in a channel is started by completion of transfer in another) Multijunction * 37-channel multifunction timer * Contains output-related timer x 11 channels, input/output-related timer x 10 channels, 16-bit input-related timer x 8 channels, and 32-bit input-related timer x 8 channels. * Capable of flexible timer configuration by mutual connection between each channel. A-D converter * 16-channel, 10-bit resolution A-D converter * Incorporates comparator mode * Can generate interrupt or start DMA transfer upon completion of A-D conversion. * Can read out conversion results in 8 or 10 bits. Serial I/O * 3-channel serial I/O * Can be set for clock-synchronized serial I/O or UART. * Capable of high-speed data transfer at 2 Mbits per second when clock synchronized or 156 Kbits per second during UART. Real-time debugger * Can rewrite or monitor the internal RAM independently of the CPU by command input from an external source. * Has its exclusive clock-synchronized serial port. Interrupt controller * Accepts and manages interrupt requests from internal peripheral I/O. * Resolves interrupt priority in 8 levels including interrupt-disabled state. Wait controller * Controls wait state for access to external extension areas. * Can insert 1 to 4 wait cycles by setting in software and extend wait period by external _________ WAIT signal. Clock PLL * Multiply-by-4 clock generator circuit * Maximum 40 MHz of CPU clock (CPU, internal ROM, internal RAM access) * Maximum 20 MHz of internal peripheral clock (peripheral module access) * Maximum external input clock frequency=10 MHz CAN JTAG * Sixteen message slots * Capable of boundary scan 1-9 32171 Group User's Manual (Rev.2.00) 1 Table 1.2.4 List of Type Name Type Name M32171F2VFP M32171F3VFP M32171F4VFP RAM Size (K bytes) 16 16 16 ROM Size (K bytes) 256 384 512 Package 144LQFP 144LQFP 144LQFP OVERVIEW 1.2 Block Diagram Number of Pins 144 144 144 1-10 32171 Group User's Manual (Rev.2.00) 1 1.3 Pin Function OVERVIEW 1.3 Pin Function Figure 1.3.1 shows pin functions of the M32171FxVFP. Table 1.3.1 explains the pin functions. 3.3V (Note 1) Clock XIN XOUT VCNT OSC-VCC OSC-VSS P70 / BCLK / WR Port 7 Reset RESET P45 / CS1 P44 / CS0 P43 / RD P42 / BHW / BHE P41 / BLW / BLE P71 / WAIT P72 / HREQ P73 / HACK 19 P20 - P27 / A23 - A30 P30 - P37 / A15 - A22 P46,P47 / A13,A14 P225 / A12 (Note2) P00 - P07 / DB0 - DB7 P10 - P17 / DB8 - DB15 P82 / TXD0 P83 / RXD0 P84 / SCLKI 0 / SCLKO 0 P85 / TXD1 P86 / RXD1 P87 / SCLKI 1 / SCLKO 1 P174 / TXD2 P175 / RXD2 P74 / RTDTXD P75 / RTDRXD P76 / RTDACK P77 / RTDCLK Port 4 Bus control Port 7 Mode MOD0 MOD1 FP 5V (Note 1) Address bus Port 2 Port 3 Port 4 Port 22 Port 0 Port 1 Port 22 CAN P220 / CTX P221 / CRX 16 Data bus 10 Port 15 Port 13 Port 12 P150,P153 / TIN0,TIN3 P130 -P137 / TIN16 -TIN23 Multi-junction timer P124-P127/ TCLK0-TCLK3 P93 - P97 / TO16 - TO20 P100 - P107 / TO8 - TO15 P110 - P117 / TO0 - TO7 AD0IN0 - AD0IN15 AVCC0 AVSS0 VREF0 M32171FxVFP 4 21 5V Serial I/O Port 8 Port 17 Port 11 Port 10 Port 9 16 A-D converter Real-time debugger Port 7 Port 6 Port 6 Interrupt controller 3 P61 - P63 P64 / SBI VCCE 4 JTMS JTCK JTRST JTDO JTDI VDD FVCC JTAG VCCI 3.3V 3 5 Note 1: 3.3V 5V VSS : denotes blocks operating with a 3.3 V power supply. : denotes blocks operating with a 5 V or 3.3 V power supply. Note 2: Use caution when using this port because it has a debug event function. Figure 1.3.1 Pin Function Diagram of 144LQFP 1-11 3.3V 32171 Group User's Manual (Rev.2.00) 1 Table 1.3.1 Description of the 32171 Pin Function (1/5) Type Power supply Pin Name Signal Name VCCE VCCI VDD FVCC VSS Clock XIN, XOUT Power supply Power supply Input/Output Function -- -- OVERVIEW 1.3 Pin Function Power supply to external I/O ports (5 V or 3.3 V). Power supply to internal logic (3.3 V). Power supply for internal RAM backup (3.3 V). Power supply for internal flash memory (3.3 V). Connect all VSS to ground (GND). Clock input/output pins. These pins contains a PLL-based frequency multiplier circuit. Apply a clock whose frequency is 1/4 the operating frequency. (When using 40 MHz CPU clock, XIN input = 10.0 MHz) RAM power supply -- Flash power supply -- Ground Clock -- Input Output ______ BCLK/WR System clock/write Output This pin outputs a clock whose frequency is twice that of external input clock. (When using 10 MHz external input clock, BCLK output = 20 MHz). Use this output when external operation needs to be synchronized. ______ If WR is selected, it indicates the byte position to which valid data is transferred when writing to an external device. OSC-VCC Power supply -- Power supply for PLL circuit. Connect OSC-VCC to the power supply rail (3.3 V). OSC-VSS Ground VCNT PLL control -- Input Connect OSC-VSS to ground. This pin controls the PLL circuit. Connect a resistor and capacitor to it. (For external circuits, refer to Section 18.1.1, "Example of an Oscillator Circuit.") ____________ Reset Mode RESET MOD0 MOD1 Reset Mode Input Input This pin resets the internal circuit. These pins set operation mode. MOD0 0 0 1 0 1 MOD1 0 1 0 0 1 Mode Single-chip mode External extension mode Processor mode (Boot mode) (Reserved) (Note1) Address A12 - A30 Address Bus Bus Output The device has 19 address lines (A12-A30) to allow two channels of up to 1 MB of memory space to be added external to the chip. A31 is not output. Note 1: For boot mode, refer to Chapter 6, "Internal Memory." 1-12 32171 Group User's Manual (Rev.2.00) 1 Table 1.3.1 Description of the 32171 Pin Function (2/5) Type Data bus Pin Name Signal Name DB0-DB15 Data bus Input/Output Function OVERVIEW 1.3 Pin Function Input/output These pins comprise 16-bit data bus to connect external devices. In write cycles, the valid byte positions to be written on the 16-bit data bus are ________ _______ ________ _______ output as BHW/BHE and BLW/BLE. In read cycles, data is always read from the 16-bit data bus. However, when transferring to the internal circuit of the M32R, only data at the valid byte positions are transferred. ___ Bus control CS0, ___ Chip select Output These pins comprise external device chip select signal. For areas for which a chip select signal is output, refer to Chapter 3, "Address Space." CS1 __ RD ___ ___ Read Output Output This signal is output when reading an external device. Indicates the byte position to which valid data is transferred ___ ___ BHW/BHE Byte high write/enable ___ ___ when writing to an external device. BHW/BHE corresponds ___ ___ BLW/BLE Byte low write/enable ____ Output to the upper address (D0-D7 is valid); BLW/BLE corresponds to the lower address (D8-D15 is valid). WAIT Wait Input When the M32R accesses an external device, a low on this ____ WAIT input extends the wait cycle. _____ HREQ Hold request Input This pin is used by an external device to request control of __________ the external bus. A low on this HREQ input causes the M32R to enter a hold state. __________ HACK Hold acknowledge Output This signal is used to notify that the M32R has entered a hold state and relinquished control of the external bus. Multijunction timer A-D converter TIN 0,TIN 3 TIN 16-TIN 23 Timer input TO 0- TO 20 Timer output TCLK 0- TCLK 3 Timer clock AVCC0 Analog power supply Input Output Input -- Input pins for multijunction timer. Output pins for the multijunction timer. Clock input pins for the multijunction timer. AVCC0 is the power supply for the A-D0 converter. Connect AVCC0 to the power supply rail (5 V or 3.3 V). AVSS0 Analog ground -- AVSS0 is analog ground for the A-D0 converter. Connect AVSS0 to the ground. 1-13 32171 Group User's Manual (Rev.2.00) 1 Table 1.3.1 Description of the 32171 Pin Function (3/5) Type A-D Pin Name Signal Name AD0IN0 Analog input Input/Output Function Input OVERVIEW 1.3 Pin Function 16-channel analog input pins for the A-D0 converter. converter - AD0IN15 VREF0 ______ voltage input Input VREF0 is the reference voltage input pin for the A-D0 converter. System break interrupt (SBI) input pin for the interrupt controller When channel 0 is in UART mode: This pin outputs a clock derived from BRG output by halving it. Interrupt controller SBI System break Input interrupt UART transmit/ Input/output receive clock output or CSIO transmit/ receive clock imput/output Serial I/O SCLKI0 / SCLKO0 When channel 0 is in CSIO mode: This pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. When channel 1 is in UART mode: This pin outputs a clock derived from BRG output by halving it. SCLKI1 / SCLKO1 UART transmit/ Input/output receive clock output or CSIO transmit/ receive clock input/output When channel 1 is in CSIO mode: This pin accepts as its input a transmit/receive clock when external clock source is selected or outputs a transmit/receive clock when internal clock source is selected. Transmit data output pin for serial I/O channel 0 Receive data input pin for serial I/O channel 0 Transmit data output pin for serial I/O channel 1. Receive data input pin for serial I/O channel 1. Transmit data output pin for serial I/O channel 2. Receive data input pin for serial I/O channel 2. Serial data output pin for the real-time debugger. Serial data input pin for the real-time debugger. Serial data transmit/receive clock input pin for the real-time debugger. TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 Real-time RTDTXD debugger RTDRXD RTDCLK Transmit data output Receive data Input Transmit data Output Receive data Input Transmit data Output Receive data Input Transmit data Output Receive data Clock input Input Input RTDACK Acknowledge Output This pin outputs a low pulse synchronously with the beginning clock of the real-time debugger's serial data output word. The duration of this low pulse indicates the type of command/data that the real-time debugger has received. Flash -only FP Flash Protect Input This mode pin has a function to protect the flash memory against E/W in hardware. 1-14 32171 Group User's Manual (Rev.2.00) 1 Table 1.3.1 Description of the 32171 Pin Function (4/5) Type CAN Pin Name Signal Name CTX CRX JTAG JTMS Data output Data input Test mode Input/Output Function Output Input Input OVERVIEW 1.3 Pin Function This pin outputs data from the CAN module. This pin is used to input data to the CAN module. Test mode select input to control state transition of the test circuit. JTCK JTRST clock Test reset Input Input Clock input for the debug module and test circuit. Test reset input to initialize the test circuit asynchronously. JTDI Serial input Input This pin is used to input test instruction code or test data serially. JTDO Serial output Output This pin outputs test instruction code or test data serially. Input/ output port (Note 1) P00 - P07 Input/output port 0 P10 - P17 Input/output port 1 P20 - P27 Input/output port 2 P30 - P37 Input/output port 3 P41 - P47 Input/output port 4 P61 - P64 Input/output port 6 P70 - P77 Input/output port 7 P82 - P87 Input/output port 8 P93 - P97 Input/output port 9 P100 - P107 P110 - P117 Input/output port 10 Input/output port 11 Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. ______ (However, P64 is a SBI input-only port.) Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Note 1: Input/output port 5 is reserved for future use. 1-15 32171 Group User's Manual (Rev.2.00) 1 Table 1.3.1 Description of the 32171 Pin Function (5/5) Type Input/ output port (Note 1) OVERVIEW 1.3 Pin Function Pin Name Signal Name P124 - P127 P130 - P137 P150, P153 P174, P175 Input/output port 12 Input/output port 13 Input/output port 15 Input/output port 17 Input/Output Function Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. Input/output Programmable input/output port. P220,P221 Input/output P225(Note 2) port 22 Input/output Programmable input/output port. (However, P221 is a CAN input only port.) Note 1: For the 32171, input/output ports 14, 16, 18, 19, 20, and 21 are nonexistent. Note 2: Use caution when using P225 because they have a debug event function. 1-16 32171 Group User's Manual (Rev.2.00) 1 1.4 Pin Layout OVERVIEW 1.4 Pin Layout Figure 1.4.1 shows pin assignments on the M32171FxVFP. Table 1.4.1 lists the pin assignments. VDD P102/TO10 P101/TO9 P100/TO8 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 VSS VCCE FP MOD1 MOD0 RESET P97/TO20 P96/TO19 P95/TO18 P94/TO17 P93/TO16 P77/RTDCLK P76/RTDACK P75/RTDRXD P74/RTDTXD P73/ HACK P72/ HREQ P71/ WAIT P70/BCLK / WR JTMS JTCK JTRST JTDO JTDI P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 P124/TCLK0 P125/TCLK1 P126/TCLK2 P127/TCLK3 VCCI P130/TIN16 P131/TIN17 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 VCCE P150/TIN0 P153/TIN3 P41/ BLW / BLE P42/ BHW / BHE VCCI VSS P43/ RD P44/ CS0 P45/ CS1 P46/A13 P47/A14 P220/CTX 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P64/ SBI P63 P62 P61 FVCC M32171FxVFP 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VSS P87/SCLKI1/SCLKO1 P86/RXD1 P85/TXD1 P84/SCLKI0/SCLKO0 P83/RXD0 P82/TXD0 VCCE P175/RXD2 P174/TXD2 VSS VCCI AVSS0 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 AVCC0 VREF0 P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 (Note) Note: * Use caution when using these pins because they have a debug event function. Figure 1.4.1 Pin Layout Diagram of the M32171FxVFP (Top View) P221/CRX P225/A12 OSC-VSS XIN XOUT OSC-VCC VCNT P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 P20/A23 P21/A24 P22/A25 P23/A26 VCCE VSS Package: 144P6Q (0.5 mm pitch) 1-17 P24/A27 P25/A28 P26/A29 P27/A30 P00/DB0 P01/DB1 P02/DB2 P03/DB3 P04/DB4 P05/DB5 P06/DB6 P07/DB7 P10/DB8 P11/DB9 P12/DB10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 32171 Group User's Manual (Rev.2.00) 1 Table 1.4.1 Pin Assignments of the M32171FxVFP No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OVERVIEW 1.4 Pin Layout Pin Name P221/CRX P225/A12 OSC-VSS XIN XOUT OSC-VCC VCNT P30 / A15 P31 / A16 P32 / A17 P33 / A18 P34 / A19 P35 / A20 P36 / A21 P37 / A22 P20 / A23 P21 / A24 P22 / A25 P23 / A26 VCCE VSS P24 / A27 P25 / A28 P26 / A29 P27 / A30 P00 / DB0 P01 / DB1 P02 / DB2 P03 / DB3 P04 / DB4 P05 / DB5 P06 / DB6 P07 / DB7 P10 / DB8 P11 / DB9 P12 / DB10 P13 / DB11 P14 / DB12 P15 / DB13 P16 / DB14 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name P17 / DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI VSS P174 / TXD2 P175 / RXD2 VCCE P82 / TXD0 P83 / RXD0 P84 / SCLKI0 / SCLKO0 P85 / TXD1 P86 / RXD1 P87 / SCLKI1 / SCLKO1 VSS FVCC P61 P62 P63 P64 / SBI P70/ BCLK / WR P71 / WAIT P72 / HREQ No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name P73/ HACK P74 / RTDTXD P75 / RTDRXD P76 / RTDACK P77 / RTDCLK P93 / TO16 P94 / TO17 P95 / TO18 P96 / TO19 P97 / TO20 RESET MOD0 MOD1 FP VCCE VSS P110 / TO0 P111 / TO1 P112 / TO2 P113 / TO3 P114 / TO4 P115 / TO5 P116 / TO6 P117 / TO7 P100 / TO8 P101 / TO9 P102 / TO10 VDD JTMS JTCK JTRST JTDO JTDI P103 / TO11 P104 / TO12 P105 / TO13 P106 / TO14 P107 / TO15 P124 / TCLK0 P125 / TCLK1 No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name P126 / TCLK2 P127 / TCLK3 VCCI P130 / TIN16 P131 / TIN17 P132 / TIN18 P133 / TIN19 P134 / TIN20 P135 / TIN21 P136 / TIN22 P137 / TIN23 VCCE P150 / TIN0 P153 / TIN3 P41 / BLW / BLE P42 / BHW / BHE VCCI VSS P43 / RD P44 / CS0 P45 / CS1 P46 / A13 P47 / A14 P220 / CTX 1-18 32171 Group User's Manual (Rev.2.00) CHAPTER 2 CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 CPU Registers General-purpose Registers Control Registers Accumulator Program Counter Data Formats Precautions on CPU 2 2.1 CPU Registers CPU 2.1 CPU Registers The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 General-purpose Registers General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are used to hold data and base addresses. Especially, R14 is used as a link register, and R15 is used as a stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the Processor Status Word register (PSW)'s stack mode (SM) bit. 0 31 0 31 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note) Note: * The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer (SPU) depending on the value of the PSW's SM bit. Figure 2.2.1 General-purpose Registers 2-2 32171 Group User's Manual (Rev.2.00) 2 2.3 Control Registers CPU 2.3 Control Registers There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers. CRn CR0 CR1 CR2 CR3 CR6 Control Registers 0 31 PSW CBR SPI SPU BPC Processor status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer Backup PC Notes: * CRn (n = 0-3, 6) denotes control register numbers. : * Dedicated "MVTC" and "MVFC" instructions are used to set and read the control registers. Figure 2.3.1 Control Registers 2-3 32171 Group User's Manual (Rev.2.00) 2 2.3.1 Processor Status Word Register: PSW (CR0) CPU 2.3 Control Registers The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs. The PSW field consists of several bits labeled Stack Mode (SM), Interrupt Enable (IE), and Condition bit (C). The BPSW field consists of backup bits of the foregoing, i.e., Backup SM bit (BSM), Backup IE bit (BIE), and Backup C bit (BC). BPSW field 0(MSB) 7 8 15 16 17 23 24 25 PSW field 31(LSB) PSW 0000000000000000 00000 00000 BSM BIE BC SM IE C (Note 1) D 16 Bit Name BSM (Backup SM) Function Holds the value of SM bit when EIT is accepted. 17 BIE (Backup IE) Holds the value of IE bit when EIT is accepted. 23 BC (Backup C) Holds the value of C bit when EIT is accepted. 24 SM (Stack Mode) 0: Interrupt stack pointer is used. 1: User stack pointer is used. 25 IE (Interrupt Enable) 0: No interrupt is accepted. 1: Interrupt is accepted. 31 C (Condition bit) Depending on instruction execution, it indicates whether operation resulted in a carry, borrow, or overflow. Note 1: "Initial" shows the state immediately after reset, R = O means the register is readable, W = O means the register is writable. Note: * For changes of the state of each bit when an EIT event occurs, refer to Chapter 4, "EIT." 0 0 0 Indeterminate Indeterminate Initial Indeterminate R W 2-4 32171 Group User's Manual (Rev.2.00) 2 2.3.2 Condition Bit Register: CBR (CR1) CPU 2.3 Control Registers The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register is a read-only register (writes to this register by "MVTC" instruction are ignored). 0(MSB) 31(LSB) CBR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 2.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3) The Interrupt Stack Pointer (SPI) and User Stack Pointer (SPU) hold the current address of the stack pointer. These registers can be accessed as general-purpose register R15. In this case, whether R15 is used as SPI or as SPU depends on the PSW's Stack Mode (SM) bit. 0(MSB) 31(LSB) SPI 0(MSB) SPI 31(LSB) SPU SPU 2.3.4 Backup PC: BPC (CR6) The Backup PC (BPC) is a register used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to 0. When an EIT occurs, the value held in the PC immediately before the EIT occurred or the value of the next instruction is set in this register. When the "RTE" instruction is executed, the saved value is returned from the BPC to the PC. However, the two low-order bits of the PC when thus returned are always fixed to "00" (control always returns to word boundaries.) 0(MSB) 31(LSB) BPC BPC 0 2-5 32171 Group User's Manual (Rev.2.00) 2 2.4 Accumulator CPU 2.4 Accumulator The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits 0--7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL." Note that when executing this instruction, the value of the accumulator is destroyed. The "MVTACHI" and "MVTACLO" instructions are used to write to the accumulator. The "MVTACHI" instruction writes data to the 32 high-order bits (bits 0-31), and the "MVTACLO" instruction writes data to the 32 low-order bits (bits 32-63). The "MVFACHI," "MVFACLO," and "MVFACMI" instructions are used to read data from the accumulator. The "MVFACHI" instruction reads data from the 32 high-order bits (bits 0-31), the "MVFACLO" instruction reads data from the 32 low-order bits (bits 32-63), and the "MVFACHI" instruction reads data from the 32 middle bits (bits 16-47). (Note 1) 0(MSB) 78 15 16 Range of bits read by MVFACMI instruction 31 32 47 48 63(LSB) ACC Range of bits read/written to by MVFACHI/MVTACHI instructions Range of bits read/written to by MVFACLO/MVTACLO instructions Note 1: Bits 0-7 always show the sign-extended value of bit 8. Writes to this bit field are ignored. 2.5 Program Counter The Program Counter (PC) is a 32-bit counter used to hold the address of the currently executed instruction. Because M32R instructions each start from an even address, the LSB (bit 31) is always 0. 0(MSB) 31(LSB) PC PC 0 2-6 32171 Group User's Manual (Rev.2.00) 2 2.6 Data Formats 2.6.1 Data Types CPU 2.6 Data Formats There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements. 0(MSB) 7(LSB) Signed byte (8-bit) integer S 0(MSB) 7(LSB) Unsigned byte (8-bit) integer 0(MSB) 15(LSB) Signed halfword (16-bit) S integer 0(MSB) 15(LSB) Unsigned halfword (16-bit) integer 0(MSB) 31(LSB) Signed word (32-bit) integer S 0(MSB) 31(LSB) Unsigned word (32-bit) integer S : Sign bit Figure 2.6.1 Data Types 2-7 32171 Group User's Manual (Rev.2.00) 2 2.6.2 Data Formats (1) Data formats in register CPU 2.6 Data Formats Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is signextended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit) data before being stored in the register. When storing data from M32R register into memory, the register data is stored in memory in different sizes depending on the instructions used. The ST instruction stores the entire 32-bit data of the register, the STH instruction stores the least significant 16-bit data, and the STB instruction stores the least significant 8-bit data. 0(MSB) Sign-extended (LDB instruction) or zero-extended (LDUB instruction) From memory (LDB, LDUB instructions) 24 31(LSB) Rn Sign-extended (LDH instruction) or zero-extended (LDUH instruction) 0(MSB) 16 Byte From memory (LDH, LDUH instructions) 31(LSB) Rn Halfword From memory (LD instructions) 0(MSB) 31(LSB) Rn Word 0(MSB) 24 31(LSB) Rn Byte To memory (STB instruction) 0(MSB) 16 31(LSB) Rn Halfword To memory (STH instruction) 0(MSB) 31(LSB) Rn Word To memory (ST instruction) Figure 2.6.2 Data Formats in Register 2-8 32171 Group User's Manual (Rev.2.00) 2 (2) Data formats in memory CPU 2.6 Data Formats Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where the LSB address bit = "0"), and word data must be located at word boundaries (where two LSB address bits = "00"). If an attempt is made to access memory data across these halfword or word boundaries, an address exception is generated. Address + 0 address 0 + 1 address + 2 address + 3 address 31 78 15 16 23 24 Byte Byte Byte Byte Byte (MSB) (LSB) Halfword Halfword Halfword (MSB) (LSB) Word Word Figure 2.6.3 Data Formats in Memory 2-9 32171 Group User's Manual (Rev.2.00) 2 (3) Endian CPU 2.6 Data Formats The following shows the generally used endian methods and the M32R family endian. Bit endian (H'01) MSB LSB MSB Byte endian (H'01234567) LSB Big endian B'0000001 D0 MSB H'01 HH MSB H'23 HL H'45 LH H'67 LL LSB D7 LSB Little endian B'0000001 D7 D0 H'67 LL H'45 LH H'23 HL H'01 HH Note: * Even for bit big endian, H'01 is not B'10000000. Figure 2.6.4 Endian Methods MPU name Endian (Bit/Byte) Address Data arrangement Bit number Ex:0x01234567 +0 MSB LL 7700 family M16C family Little/Little +1 +2 L LH HL Competition M32R family M16 family Big/Big +3 L SB LL Little/Big +3 SB HH +0 MSB HH +1 +2 +0 MSB HH +1 +2 L +3 SB LL HL LH HL LH 31-24 23-16 15-8 7-0 0 31-24 23-16 15-8 7-0 -7 8-15 16-23 24-31 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 Note: * The M32R's endian method is big endian for both bit and byte . Figure 2.6.5 M32R Family Endian 2-10 32171 Group User's Manual (Rev.2.00) 2 (4) Transfer instructions * Constant transfer LD24 Rdest, #imm24 imm24 CPU 2.6 Data Formats LD24 LDI LDI Rdest, #imm24 Rdest, #imm16 Rdest, #imm8 0 23 Rdest 0 00 8 31 SETH Rdest, #imm16 SETH Rdest, #imm16 imm16 0 15 Rdest 0 15 00 00 31 * Register to register transfer MV MV Rdest, Rsrc Rsrc 0 31 Rdest, Rsrc Rdest 0 31 * Control register transfer MVTC Rsrc, CRdest MVFC Rdest, CRsrc MVTC Rsrc, CRdest Rsrc 0 31 CRdest 0 31 Note: * For the MVTC instruction, the condition bit C does not change unless CRdest is CR0 (PSW) . Figure 2.6.6 Transfer instructions 2-11 32171 Group User's Manual (Rev.2.00) 2 (5) Memory (signed) to register transfer Memory * Signed 32 bits LD24 LD Rsrc, #label Rdest, @Rsrc label Rdest CPU 2.6 Data Formats Register +0 +1 +2 +3 0 31 * Signed 16 bits label LD24 LDH Rsrc, #label Rdest, @Rsrc Rdest +0 +1 +2 +3 00 FF 0 00 FF 31 Check the MSB 0 = positive 1 = negative * Signed 8 bits label Rdest +0 +1 +2 +3 LD24 LDB Rsrc, #label Rdest, @Rsrc 00 FF 0 00 FF 00 FF 31 Check the MSB 0 = positive 1 = negative Figure 2.6.7 Memory (signed) to register transfer (6) Memory (unsigned) to register transfer * Unsigned 32 bits LD24 LD Rsrc, #label Rdest, @Rsrc label Memory Rdest Register +0 +1 +2 +3 0 31 * Unsigned 16 bits label LD24 Rsrc, #label LDUH Rdest, @Rsrc +0 +1 +2 +3 Rdest 00 0 00 31 * Unsigned 8 bits label Rdest LD24 Rsrc, #label LDUB Rdest, @Rsrc +0 +1 +2 +3 0 00 00 00 31 Figure 2.6.8 Memory (unsigned) to register transfer 2-12 32171 Group User's Manual (Rev.2.00) 2 (7) Things to be noted for data transfer CPU 2.6 Data Formats Note that in data transfer, data arrangements in registers and those in memory are different. Data in register (R0-R15) +0 HL LH LL D31 HH D0 Data in memory +1 HL +2 LH +3 LL D31 Word data (32 bits) D0 HH MSB (R0-R15) LSB MSB +0 +1 L D15 +2 LSB +3 Half-word data (16 bits) D0 H L D31 D0 H MSB (R0-R15) LSB MSB +0 LSB +1 +2 +3 Byte data (8 bits) D0 D31 D0 D7 MSB LSB MSB LSB Figure 2.6.9 Difference in Data Arrangements 2-13 32171 Group User's Manual (Rev.2.00) 2 2.7 Precautions on CPU * Usage Notes for 0 Division Instruction Problem and Conditions CPU 2.7 Precautions on CPU Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction under the conditions described in (1). (1) If 0 division calculation is executed when the divisor = 0 for instructions DIV, DIVU, REM and REMU, (2) the result will be inaccurate calculations for any of the following instructions that are executed immediately after 0 division: ADDV, ADDX, ADD, ADDI, ADDV3, ADD3, CMP, CMPU, CMPI, CMPUI, SUBV, SUBX, SUB, DIV, DIVU, REM, REMU. Countermeasure Assuming that the 0 division occurrence itself is not expected by the system and therefore is the cause of miscalculations, before executing division or remainder instructions, do a 0 check on the divisor to make sure 0 division does not occur. 2-14 32171 Group User's Manual (Rev.2.00) CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space 3.2 Operation Modes 3.3 Internal ROM Area and External Extension Area 3.4 Internal RAM Area and SFR Area 3.5 EIT Vector Entry 3.6 ICU Vector Table 3.7 Notes on Address Space 3 3.1 Outline of Address Space ADDRESS SPACE 3.1 Outline of Address Space The M32R's logical addresses are always handled in 32 bits, providing 4 Gbytes of linear address space. The M32R/E's address space consists of the following: (1) User space * Internal ROM area * External extension area * Internal RAM area * Special Function Register (SFR) area (2) Boot program space (3) System space (areas not open to the user) (1) User space A 2 Gbytes of address space from H'0000 0000 to H'7FFF FFFF is the user space. Located in this space are the internal ROM area, external extension area, internal RAM area, and Special Function Register (SFR) area, an area containing a group of internal peripheral I/O registers. Of these, the internal ROM and external extension areas are located differently depending on mode settings which will be described later. (2) Boot program space A 1 Gbyte of address space from H'8000 0000 to H'BFFF FFFF is the boot program space. This space stores a program (boot program) which enables on-board programming when the internal flash area is blank. (3) System space A 1 Gbyte of address space from H'C000 0000 to H'FFFF FFFF is the system space. This space is reserved for use by development tools such as an in-circuit emulator or a debug monitor, and cannot be used by the user. 3-2 32171 Group User's Manual (Rev.2.00) 3 Logical address H'0000 0000 (16 Mbytes) ADDRESS SPACE 3.1 Outline of Address Space External extension area (4 Mbytes) EIT vector entry H'0000 0000 Internal ROM area (Note 1) Reserved area (512 Kbytes) H'000F FFFF H'0010 0000 H'0007 FFFF H'0008 0000 2 Gbytes User space CS0 area (1 Mbyte) Ghost area in units of 16 Mbytes H'001F FFFF H'0020 0000 CS1 area (1 Mbyte) H'002F FFFF H'0030 0000 Ghost area in CS1 (1 Mbyte) H'7FFF FFFF H'8000 0000 BOOT ROM area (8 Kbytes) Reserved area (8 Kbytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16 Kbytes) Ghost area in units of 16 Kbytes H'003F FFFF H'0040 0000 Ghost area in 4 Mbytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM area (16 Kbytes) H'0080 7FFF H'0080 8000 Reserved area (96 Kbytes) 1 Gbyte Boot program space (Note 2) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1 Gbyte System space Ghost area in units of 128 Kbytes H'FFFF FFFF H'00FF FFFF Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0. Figure 3.1.1 Address Space of the M32171F4 3-3 32171 Group User's Manual (Rev.2.00) 3 Logical address H'0000 0000 (16 Mbytes) ADDRESS SPACE 3.1 Outline of Address Space External extension area (4 Mbytes) EIT vector entry H'0000 0000 Internal ROM area (Note 1) H'0005 FFFF H'0006 0000 Reserved area (640 Kbytes) H'000F FFFF H'0010 0000 CS0 area (1 Mbyte) Ghost area in units of 16 Mbytes H'001F FFFF H'0020 0000 CS1 area (1 Mbyte) H'002F FFFF H'0030 0000 Ghost area in CS1 (1 Mbyte) 2 Gbytes User space H'7FFF FFFF H'8000 0000 BOOT ROM area (8 Kbytes) Reserved area (8 Kbytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16 Kbytes) Ghost area in units of 16 Kbytes H'003F FFFF H'0040 0000 Ghost area in 4 Mbytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM area (16 Kbytes) H'0080 7FFF H'0080 8000 Reserved area (96 Kbytes) 1 Gbyte Boot program space (Note 2) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1 Gbyte System space Ghost area in units of 128 Kbytes H'FFFF FFFF H'00FF FFFF Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0. Figure 3.1.2 Address Space of the M32171F3 3-4 32171 Group User's Manual (Rev.2.00) 3 Logical address H'0000 0000 (16 Mbytes) ADDRESS SPACE 3.1 Outline of Address Space External extension area (4 Mbytes) EIT vector entry H'0000 0000 Internal ROM area (Note 1) H'0003 FFFF H'0004 0000 Reserved area (768 Kbytes) H'000F FFFF H'0010 0000 2 Gbytes User space CS0 area (1 Mbyte) Ghost area in units of 16 Mbytes H'001F FFFF H'0020 0000 CS1 area (1 Mbyte) H'002F FFFF H'0030 0000 Ghost area in CS1 (1 Mbyte) H'7FFF FFFF H'8000 0000 BOOT ROM area (8 Kbytes) Reserved area (8 Kbytes) H'8000 0000 H'8000 1FFF H'8000 2000 H'8000 3FFF H'8000 4000 SFR area (16 Kbytes) Ghost area in units of 16 Kbytes H'003F FFFF H'0040 0000 Ghost area in 4 Mbytes H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000 Internal RAM area (16 Kbytes) H'0080 7FFF H'0080 8000 Reserved area (96 Kbytes) 1 Gbyte Boot program space (Note 2) H'BFFF FFFF H'C000 0000 H'BFFF FFFF H'0081 FFFF H'0082 0000 1 Gbyte System space Ghost area in units of 128 Kbytes H'FFFF FFFF H'00FF FFFF Note 1: This location varies with chip mode settings. Note 2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0. Figure 3.1.3 Address Space of the M32171F2 3-5 32171 Group User's Manual (Rev.2.00) 3 3.2 Operation Modes ADDRESS SPACE 3.2 Operation Modes The 32171 is placed in one of the following modes by setting its operation mode (using MOD0 and MOD1 pins). For details about the mode used to rewrite the internal flash memory, refer to Section 6.5, "Programming of Internal Flash Memory." Table 3.2.1 Setting Operation Modes MOD0 VSS VSS VCCE VCCE MOD1 (Note 1) VSS VCCE VSS VCCE Operation Mode (Note 2) Single-chip mode External extension mode Processor mode (FP = VSS) Reserved (cannot be used) Note 1: VCCE connects to +5 V or +3.3 V, and VSS connects to GND. Note 2: For flash rewrite mode (FP = VCCE) not listed in the above table, refer to Section 6.5, "Programming of Internal Flash Memory." The internal ROM and external extension areas are located differently depending on the 32171's operation mode. (All other areas in address space are located the same way.) The address maps of internal ROM and external extension areas in each mode are shown below. (For flash rewrite mode (FP = VCCE) not listed in the above table, refer to Section 6.5, "Programming of Internal Flash Memory.") Non-CS0 area H'0000 0000 H'0007 FFFF H'0008 0000 H'000F FFFF H'0010 0000 External extension area Internal ROM area (512 Kbytes) Internal ROM area (512 Kbytes) Reserved area (512 Kbytes) CS0 area (1 Mbytes) CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 External extension area Ghost area in CS0 (1 Mbyte) CS1 area (1 Mbytes) CS1 area (1 Mbytes) H'002F FFFF H'0030 0000 Ghost area in CS1 (1 Mbyte) H'003F FFFF Ghost area in CS1 (1 Mbyte) Figure 3.2.1 M32171F4 Operation Mode and Internal ROM/External Extension Areas 3-6 32171 Group User's Manual (Rev.2.00) 3 Non-CS0 area H'0000 0000 H'0005 FFFF H'0006 0000 H'000F FFFF H'0010 0000 CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 External extension area ADDRESS SPACE 3.2 Operation Modes Internal ROM area (384 Kbytes) Internal ROM area (384 Kbytes) Reserved area (640 Kbytes) External extension area CS0 area (1 Mbytes) Ghost area in CS0 (1 Mbytes) CS1 area (1 Mbytes) CS1 area (1 Mbytes) H'002F FFFF H'0030 0000 Ghost area in CS1 (1 Mbytes) Ghost area in CS1 (1 Mbytes) H'003F FFFF Figure 3.2.2 M32171F3 Operation Mode and Internal ROM/External extension Areas Non-CS0 area H'0000 0000 H'0003 FFFF H'0004 0000 Internal ROM area (256 Kbytes) Internal ROM area (256 Kbytes) Reserved area (768 Kbytes) CS0 area (1 Mbytes) External extension area H'000F FFFF H'0010 0000 CS0 area (1 Mbyte) H'001F FFFF H'0020 0000 Ghost area in CS0 (1 Mbytes) External extension area CS1 area (1 Mbytes) CS1 area (1 Mbytes) H'002F FFFF H'0030 0000 Ghost area in CS1 (1 Mbytes) Ghost area in CS1 (1 Mbytes) H'003F FFFF Figure 3.2.3 M32171F2 Operation Mode and Internal ROM/External extension Areas 3-7 32171 Group User's Manual (Rev.2.00) 3 ADDRESS SPACE 3.3 Internal ROM/External Extension Areas 3.3 Internal ROM Area and External Extension Area The 8 Mbyte area at addresses H'0000 0000 to H'007F FFFF in the user space accommodates the internal ROM and external extension areas. Of this, a 4 Mbytes of address space from H'0000 0000 to H'003F FFFF is the area that the user can actually use. All other areas here comprise a 4 Mbytes of ghost area. (When programming, do not use this ghost area intentionally.) For details on how the internal ROM and external extension areas are located differently depending on the 32171's operation modes set, refer to Section 3.2, "Operation Modes." 3.3.1 Internal ROM Area The internal ROM is located in the area shown below. Also, this area has an EIT vector entry (and ICU vector table) located in it at the beginning. Table 3.3.1 Addresses at Which the 32171's Internal ROM is Located Type Name M32171F4 M32171F3 M32171F2 Size 512 Kbytes 384 Kbytes 256 Kbytes Located address H'0000 0000 - H'0007 FFFF H'0000 0000 - H'0005 FFFF H'0000 0000 - H'0003 FFFF 3.3.2 External Extension Area An external extension area is provided only when external extension mode or processor mode has been selected when setting the 32171's operation mode. For access to this external extension area, the 32171 outputs the control signals necessary to access external devices. ________ _______ The 32171's CS0 and CS1 signals are output corresponding to the address mapping of the external ________ _______ extension area. The CS0 signal is output for the CS0 area, and the CS1 signal is output for the CS1 area. Table 3.3.2 Address Mapping of the External Extension Area in Each Operation Mode of the 32171 Operation Mode Single-chip mode External extension mode Address mapping of the external extension area None Addresses H'0010 0000 to H'001F FFFF (CS0 area: 1 Mbytes) Addresses H'0020 0000 to H'002F FFFF (CS1 area: 1 Mbytes) (Note 1) Processor mode Addresses H'0000 0000 to H'000F FFFF (CS0 area: 1 Mbytes) (Note 2) Addresses H'0020 0000 to H'002F FFFF (CS1 area: 1 Mbytes) (Note 2) Note 1: During external extension mode, a ghost (1 Mbyte) of the CS1 area appears in an area of H'0030 0000 through H'003F FFFF. Note 2: During processor mode, a ghost (1 Mbyte) of the CS0 area appears in an area of H'0010 0000 through H'001F FFFF and a ghost (1 Mbyte) of the CS1 area appears in an area of H'0030 0000 through H'003F FFFF. 3-8 32171 Group User's Manual (Rev.2.00) 3 3.4 Internal RAM Area and SFR Area ADDRESS SPACE 3.4 Internal RAM/SFR Areas The 8 Mbyte area at addresses H'0080 0000 to H'00FF FFFF in the user space accommodates the internal RAM area and Special Function Register (SFR) area. Of this, a 128 Kbytes of address space from H'0080 0000 to H'0081 FFFF is the area that the user can actually use. All other areas here comprise a ghost area in units of 128 Kbytes. (When programming, do not use this ghost area intentionally.) 3.4.1 Internal RAM Area The internal RAM (16-Kbyte) is allocated to the addresses H'0080 4000 through H'0080 7FFF. 3.4.2 Special Function Register (SFR) Area Addresses H'0080 0000 to H'0080 3FFFF are the Special Function Register (SFR) area. This area has registers for internal peripheral I/O located in it. H'0080 0000 SFR area (16 Kbytes) H'0080 3FFF H'0080 4000 Virtual-flash emulation areas separated in units of 8 Kbytes or 4 Kbytes can be allocated here. For details, refer to Section 6.7. Internal RAM (16 Kbytes) H'0080 7FFF Figure 3.4.1 Internal RAM Area and Special Function Register (SFR) Area 3-9 32171 Group User's Manual (Rev.2.00) 3 0 H'0080 0000 Interrupt controller (ICU) H'0080 007E H'0080 0080 H'0080 00EE H'0080 0100 Serial I/O0 H'0080 0146 H'0080 0FFE H'0080 1000 78 +0 address ADDRESS SPACE 3.4 Internal RAM/SFR Areas 15 H'0080 07E0 0 78 +0 address 15 +1 address +1 address Flash control H'0080 07F2 A-D0 converter H'0080 0FE0 MJT (TML1) Multijunction timer (MJT) CAN0 H'0080 0180 Wait controller H'0080 11FE H'0080 0200 MJT (common part) H'0080 023E H'0080 0240 MJT (TOP) H'0080 02FE H'0080 0300 MJT (TIO) H'0080 03BE H'0080 03C0 MJT (TMS) H'0080 03D8 Multijunction timer (MJT) H'0080 3FFE H'0080 03 E0 H'0080 03FE H'0080 0400 H'0080 0478 MJT (TML0) DMAC H'0080 0700 Input/output port H'0080 0756 H'0080 0760 Note: The Real-time Debugger (RTD) is designed to be an independent module operated from an external source, and is transparent to the CPU. Figure 3.4.2 Outline Address Mapping of the SFR Area 3-10 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 Interrupt Mask Register (IMASK) SBI Control Register (SBICR) +0 Address D7 D8 Interrupt Vector Register (IVECT) ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 H'0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) H'0080 0062 H'0080 0064 H'0080 0066 H'0080 0068 SIO2,3 Transmit/Receive Interrupt Control Register (ISO23CR) H'0080 006A H'0080 006C A-D0 Conversion Interrupt Control Register (IAD0CCR) H'0080 006E SIO0 Receive Interrupt Control Register (ISIO0RXCR) H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E H'0080 0080 H'0080 0082 H'0080 0084 H'0080 0086 H'0080 0088 H'0080 008A H'0080 008C A-D0 Comparate Data Register (AD0CMP) A-D0 Successive Approximation Register (AD0SAR) A-D0 Scan Mode Register 0 (AD0SCM0) A-D0 Scan Mode Register 1 (AD0SCM1) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 4 (IMJTICR4) A-D0 Single Mode Register 0 (AD0SIM0) A-D0 Single Mode Register 1 (AD0SIM1) SIO1 Receive Interrupt Control Register (ISIO1RXCR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register 6 (IMJTOCR6) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 1 (IMJTOCR1) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register 5 (IMJTOCR5) MJT Output Interrupt Control Register 7 (IMJTOCR7) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 3 (IMJTICR3) RTD Interrupt Control Register (IRTDCR) DMA5-9 Interrupt Control Register (IDMA59CR) H'0080 0090 H'0080 0092 H'0080 0094 H'0080 0096 H'0080 0098 H'0080 009A H'0080 009C H'0080 009E H'0080 00A0 H'0080 00A2 H'0080 00A4 H'0080 00A6 H'0080 00A8 H'0080 00AA H'0080 00AC H'0080 00AE 10-bit A-D0 Data Register 0 (AD0DT0) 10-bit A-D0 Data Register 1 (AD0DT1) 10-bit A-D0 Data Register 2 (AD0DT2) 10-bit A-D0 Data Register 3 (AD0DT3) 10-bit A-D0 Data Register 4 (AD0DT4) 10-bit A-D0 Data Register 5 (AD0DT5) 10-bit A-D0 Data Register 6 (AD0DT6) 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) 10-bit A-D0 Data Register 12 (AD0DT12) 10-bit A-D0 Data Register 13 (AD0DT13) 10-bit A-D0 Data Register 14 (AD0DT14) 10-bit A-D0 Data Register 15 (AD0DT15) H'0080 00D0 Blank addresses are reserved areas. 8-bit A-D0 Data Register 0 (AD08DT0) Figure 3.4.3 Register Mapping of the SFR Area (1) 3-11 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 H'0080 00DA H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E2 H'0080 00E4 H'0080 00E6 H'0080 00E8 H'0080 00EA H'0080 00EC H'0080 00EE +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 4 (AD08DT4) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 11 (AD08DT11) 8-bit A-D0 Data Register 12 (AD08DT12) 8-bit A-D0 Data Register 13 (AD08DT13) 8-bit A-D0 Data Register 14 (AD08DT14) 8-bit A-D0 Data Register 15 (AD08DT15) H'0080 0100 SIO23 Interrupt Status Register (SI23STAT) SIO03 Interrupt Mask Register (SI03MASK) H'0080 0102 SIO03 Receive Interrupt Cause Select Register (SI03SEL) H'0080 0110 H'0080 0112 H'0080 0114 H'0080 0116 SIO0 Transmit Control Register (S0TCNT) SIO0 Transmit/Receive Mode Register (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB) SIO0 Receive Control Register (S0RCNT) SIO1 Baud Rate Register (S1BAUR) H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126 SIO1 Transmit Control Register (S1TCNT) SIO0 Transmit/Receive Mode Register (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register (S1RCNT) SIO1 Baud Rate Register (S1BAUR) H'0080 0130 H'0080 0132 H'0080 0134 H'0080 0136 SIO2 Transmit Control Register (S2TCNT) SIO2 Transmit/Receive Mode Register (S2MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register (S2RCNT) SIO2 Baud Rate Register (S2BAUR) H'0080 0180 Wait Cycles Control Register (WTCCR) H'0080 0200 H'0080 0202 H'0080 0204 Prescaler Register 0 (PRS0) Prescaler Register 2 (PRS2) Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 1 (PRS1) Output Event Bus Control Register (OEBCR) H'0080 0210 H'0080 0212 H'0080 0214 TCLK Input Processing Control Register (TCLKCR) TIN Input Processing Control Register 0 (TINCR0) Blank addresses are reserved areas. Figure 3.4.4 Register Mapping of the SFR Area (2) 3-12 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 0216 H'0080 0218 H'0080 021A H'0080 021C H'0080 021E H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A F/F Source Select Register 0 (FFS0) +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 TIN Input Processing Control Register 3 (TINCR3) TIN Input Processing Control Register 4 (TINCR4) F/F Source Select Register 1 (FFS1) F/F Protect Register 0 (FFP0) F/F Data Register 0 (FFD0) F/F Protect Register 1 (FFP1) F/F Data Register 1 (FFD1) H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E H'0080 0240 H'0080 0242 H'0080 0244 H'0080 0246 TOP Interrupt Control Register 0 (TOPIR0) TOP Interrupt Control Register 2 (TOPIR2) TIO Interrupt Control Register 0 (TIOIR0) TIO Interrupt Control Register 2 (TIOIR2) TIN Interrupt Control Register 0 (TINIR0) TOP Interrupt Control Register 1 (TOPIR1) TOP Interrupt Control Register 3 (TOPIR3) TIO Interrupt Control Register 1 (TIOIR1) TMS Interrupt Control Register (TMSIR) TIN Interrupt Control Register 1 (TINIR1) TIN Interrupt Control Register 4 (TINIR4) TIN Interrupt Control Register 6 (TINIR6) TIN Interrupt Control Register 5 (TINIR5) TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) TOP0 Correction Register (TOP0CC) H'0080 0250 H'0080 0252 H'0080 0254 H'0080 0256 TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) TOP1 Correction Register (TOP1CC) H'0080 0260 H'0080 0262 H'0080 0264 H'0080 0266 TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) TOP2 Correction Register (TOP2CC) H'0080 0270 H'0080 0272 H'0080 0274 H'0080 0276 TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) TOP3 Correction Register (TOP3CC) H'0080 0280 H'0080 0282 H'0080 0284 H'0080 0286 TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) TOP4 Correction Register (TOP4CC) H'0080 0290 H'0080 0292 H'0080 0294 Blank addresses are reserved areas. TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) Figure 3.4.5 Register Mapping of the SFR Area (3) 3-13 32171 Group User's Manual (Rev.2.00) 3 Address H'0080 0296 H'0080 0298 H'0080 029A H'0080 029C H'0080 029E H'0080 02A0 H'0080 02A2 H'0080 02A4 H'0080 02A6 H'0080 02A8 H'0080 02AA TOP6, 7 Control Register (TOP67CR) TOP6 Correction Register (TOP6CC) TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) TOP0-5 Control Register 0 (TOP05CR0) D0 +0 Address D7 D8 TOP5 Correction Register (TOP5CC) ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Addres s D15 TOP0-5 Control Register 1 (TOP05CR1) H'0080 02B0 H'0080 02B2 H'0080 02B4 H'0080 02B6 TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) TOP7 Correction Register (TOP7CC) H'0080 02C0 H'0080 02C2 H'0080 02C4 H'0080 02C6 TOP8Counter (TOP8CT) TOP8 Reload Register (TOP8RL) TOP8 Correction Register (TOP8CC) H'0080 02D0 H'0080 02D2 H'0080 02D4 H'0080 02D6 TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) TOP9 Correction Register (TOP9CC) H'0080 02E0 H'0080 02E2 H'0080 02E4 H'0080 02E6 H'0080 02E8 H'0080 02EA TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) TOP10 Correction Register (TOP10CC) TOP8-10 Control Register (TOP810CR) H'0080 02FA H'0080 02FC H'0080 02FE H'0080 0300 H'0080 0302 H'0080 0304 H'0080 0306 TOP0-10 External Enable Register (TOPEEN) TOP0-10 Enable Protect Register (TOPPRO) TOP0-10 Count Enable Register (TOPCEN) TIO0 Counter (TIO0CT) TIO0 Reload Register (TIO0RL1) TIO0 Reload 0/Measure Register (TIO0RL0) H'0080 0310 H'0080 0312 H'0080 0314 H'0080 0316 H'0080 0318 H'0080 031A Blank addresses are reserved areas. . TIO1 Counter (TIO1CT) TIO1 Reload Register (TIO1RL1) TIO1 Reload 0/Measure Register (TIO1RL0) TIO0-3 Control Register 0 (TIO03CR0) Figure 3.4.6 Register Mapping of the SFR Area (4) 3-14 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 031C +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 TIO0-3 Control Register 1 (TIO03CR1) H'0080 0320 H'0080 0322 H'0080 0324 H'0080 0326 TIO2 Counter (TIO2CT) TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/Measure Register (TIO2RL0) H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336 TIO3 Counter (TIO3CT) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/Measure Register (TIO3RL0) H'0080 0340 H'0080 0342 H'0080 0344 H'0080 0346 H'0080 0348 H'0080 034A TIO4 Control Register (TIO4CR) TIO4 Counter (TIO4CT) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/Measure Register (TIO4RL0) TIO5 Control Register (TIO5CR) H'0080 0350 H'0080 0352 H'0080 0354 H'0080 0356 TIO5 Counter (TIO5CT) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/Measure Register (TIO5RL0) H'0080 0360 H'0080 0362 H'0080 0364 H'0080 0366 H'0080 0368 H'0080 036A TIO6 Control Register (TIO6CR) TIO6 Counter (TIO6CT) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/Measure Register (TIO6RL0) TIO7 Control Register (TIO7CR) H'0080 0370 H'0080 0372 H'0080 0374 H'0080 0376 TIO7 Counter (TIO7CT) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/Measure Register (TIO7RL0) H'0080 0380 H'0080 0382 H'0080 0384 H'0080 0386 H'0080 0388 H'0080 038A TIO8 Control Register (TIO8CR) TIO8 Counter (TIO8CT) TIO8 Reload 1 Register (TIO8RL1) TIO8 Reload 0/Measure Register (TIO8RL0) TIO9 Control Register (TIO9CR) H'0080 0390 H'0080 0392 H'0080 0394 H'0080 0396 TIO9 Counter (TIO9CT) TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/Measure Register (TIO9RL0) . Blank addresses are reserved areas. Figure 3.4.7 Register Mapping of the SFR Area (5) 3-15 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 03BC H'0080 03BE H'0080 03C0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA +0 Address D7 D8 TIO0-9 Enable Protect Register (TIOPRO) TIO0-9 Count Enable Register (TIOCEN) TMS0 Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS0 Control Register (TMS0CR) ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 TMS1 Control Register (TMS1CR) H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8 TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) H'0080 03E0 H'0080 03E2 TML0 Counter, High (TML0CTH) TML0 Counter, Low (TML0CTL) H'0080 03EA TML0 Control Register (TML0CR) H'0080 03F0 H'0080 03F2 H'0080 03F4 H'0080 03F6 H'0080 03F8 H'0080 03FA H'0080 03FC H'0080 03FE H'0080 0400 TML0 Measure 3 Register, High (TML0MR3H) TML0 Measure 3 Register, Low (TML0MR3L) TML0 Measure 2 Register, High (TML0MR2H) TML0 Measure 2 Register, Low (TML0MR2L) TML0 Measure 1 Register, High (TML0MR1H) TML0 Measure 1 Register, Low (TML0MR1L) TML0 Measure 0 Register, High (TML0MR0H) TML0 Measure 0 Register, Low (TML0MR0L) DMA0-4 Interrupt Request Status Register (DM04ITST) DMA0-4 Interrupt Mask Register (DM04ITMK) H'0080 0408 DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) Blank addresses are reserved areas. . Figure 3.4.8 Register Mapping of the SFR Area (6) 3-16 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 DMA9 Channel Control Register (DM9CNT) DMA4 Channel Control Register (DM4CNT) DMA8 Channel Control Register (DM8CNT) DMA3 Channel Control Register (DM3CNT) DMA7 Channel Control Register (DM7CNT) DMA2 Channel Control Register (DM2CNT) +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 DMA2 Transfer Count Register (DM2TCT) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA7 Transfer Count Register (DM7TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA3 Transfer Count Register (DM3TCT) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA8 Transfer Count Register (DM8TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA4 Transfer Count Register (DM4TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA9 Transfer Count Register (DM9TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P1 Data Register (P1DATA) P3 Data Register (P3DATA) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) Blank addresses are reserved areas. Figure 3.4.9 Register Mapping of the SFR Area (7) 3-17 32171 Group User's Manual (Rev.2.00) 3 Addres s H'0080 0716 D0 +0Address P22 Data Register (P22DATA) D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas Address +1 D15 H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P22 Direction Register (P22DIR) H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 P22 Operation Mode Register (P22MOD) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) Port Input Function Enable Register (PIEN) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) H'0080 077E H'0080 07E0 H'0080 07E2 H'0080 07E4 H'0080 07E6 H'0080 07E8 Bus Mode Control Register (BUSMODC) Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) Virtual-flash L Bank Register 0 (FELBANK0) Virtual-flash S Bank Register 0 (FESBANK0) Virtual-flash S Bank Register 1 (FESBANK1) H'0080 07F0 H'0080 07F2 H'0080 0FE0 H'0080 0FE2 H'0080 0FEA TML1 Counter, High (TML1CTH) TML1 Counter, Low (TML1CTL) TML1 Control Register (TML1CR) H'0080 0FF0 H'0080 0FF2 TML1 Measure 3 Register, High (TML1MR3H) TML1 Measure 3 Register, Low (TML1MR3L) Blank addresses are reserved areas. Figure 3.4.10 Register Mapping of the SFR Area (8) 3-18 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 0FF4 H'0080 0FF6 H'0080 0FF8 H'0080 0FFA H'0080 0FFC H'0080 0FFE +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 TML1 Measure 2 Register, High(TML1MR2H) TML1 Measure 2 Register, Low(TML1MR2L) TML1 Measure 1 Register, High(TML1MR1H) TML1 Measure 1 Register, Low(TML1MR1L) TML1 Measure 0 Register, High(TML1MR0H) TML1 Measure 0 Register, Low(TML1MR0L) H'0080 1000 H'0080 1002 H'0080 1004 H'0080 1006 H'0080 1008 H'0080 100A H'0080 100C H'0080 100E H'0080 1010 H'0080 1012 H'0080 1014 H'0080 1016 CAN0 Control Register (CAN0CNT) CAN0 Status Register (CAN0STAT) CAN0 Extension ID Register (CAN0EXTID) CAN0 Configuration Register (CAN0CONF) CAN0 Time Stamp Count Register (CAN0TSTMP) CAN0 Receive Error Count Register (CAN0REC) CAN0 Transmit Error Count Register (CAN0TEC) CAN0 Slot Interrupt Status Register (CAN0SLIST) CAN0 Slot Interrupt Mask Register (CAN0SLIMK) CAN0 Error Interrupt Status Register (CAN0ERIST) CAN0 Baut Rate Prescaler (CAN0BRP) CAN0 Error Interrupt Mask Register (CAN0ERIMK) H'0080 1028 CAN0 Global Mask Register Standard ID0(C0GMSKS0) CAN0 Global Mask Register Standard ID1(C0GMSKS1) H'0080 102A CAN0 Global Mask Register Extended ID0(C0GMSKE0) CAN0 Global Mask Register Extended ID1(C0GMSKE1) H'0080 102C CAN0 Global Mask Register Extended ID2(C0GMSKE2) H'0080 102E H'0080 1030 CAN0 Local Mask Register A Standard ID0(C0LMSKAS0) H'0080 1032 CAN0 Local Mask Register A Extended ID0(C0LMSKAE0) H'0080 1034 CAN0 Local Mask Register A Extended ID2(C0LMSKAE2) H'0080 1036 H'0080 1038 CAN0 Local Mask Register B Standard ID0(C0LMSKBS0) H'0080 103A CAN0 Local Mask Register B Extended ID0(C0LMSKBE0) H'0080 103C CAN0 Local Mask Register B Extended ID2(C0LMSKBE2) CAN0 Local Mask Register B Standard ID1(C0LMSKBS1) CAN0 Local Mask Register B Extended ID1(C0LMSKBE1) CAN0 Local Mask Register A Standard ID1(C0LMSKAS1) CAN0 Local Mask Register A Extended ID1(C0LMSKAE1) H'0080 1050 H'0080 1052 H'0080 1054 H'0080 1056 H'0080 1058 CAN0 Message Slot 0 Control Register (C0MSL0CNT) CAN0 Message Slot 2 Control Register (C0MSL2CNT) CAN0 Message Slot 4 Control Register (C0MSL4CNT) CAN0 Message Slot 6 Control Register (C0MSL6CNT) CAN0 Message Slot 8 Control Register (C0MSL8CNT) CAN0 Message Slot 1 Control Register (C0MSL1CNT) CAN0 Message Slot 3 Control Register (C0MSL3CNT) CAN0 Message Slot 5 Control Register (C0MSL5CNT) CAN0 Message Slot 7 Control Register (C0MSL7CNT) CAN0 Message Slot 9 Control Register (C0MSL9CNT) CAN0 Message Slot 11 Control Register (C0MSL11CNT) CAN0 Message Slot 13 Control Register (C0MSL13CNT) CAN0 Message Slot 15 Control Register (C0MSL15CNT) H'0080 105A CAN0 Message Slot 10 Control Register (C0MSL10CNT) H'0080 105C CAN0 Message Slot 12 Control Register (C0MSL12CNT) H'0080 105E CAN0 Message Slot 14 Control Register (C0MSL14CNT) Blank addresses are reserved areas. Figure 3.4.11 Register Mapping of the SFR Area (9) 3-19 32171 Group User's Manual (Rev.2.00) 3 Address D0 H'0080 1100 H'0080 1102 H'0080 1104 H'0080 1106 H'0080 1108 H'0080 110A H'0080 110C H'0080 110E H'0080 1110 H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1118 H'0080 111A H'0080 111C H'0080 111E H'0080 1120 H'0080 1122 H'0080 1124 H'0080 1126 H'0080 1128 H'0080 112A H'0080 112C H'0080 112E H'0080 1130 H'0080 1132 H'0080 1134 H'0080 1136 H'0080 1138 H'0080 113A H'0080 113C H'0080 113E H'0080 1140 H'0080 1142 H'0080 1144 H'0080 1146 H'0080 1148 H'0080 114A H'0080 114C H'0080 114E H'0080 1150 H'0080 1152 +0 Addres s D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Addres s D15 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) CAN0 Message Slot 0 Data 0 (C0MSL0DT0) CAN0 Message Slot 0 Data 2 (C0MSL0DT2) CAN0 Message Slot 0 Data 4 (C0MSL0DT4) CAN0 Message Slot 0 Data 6 (C0MSL0DT6) CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) CAN0 Message Slot 0 Data 1 (C0MSL0DT1) CAN0 Message Slot 0 Data 3 (C0MSL0DT3) CAN0 Message Slot 0 Data 5 (C0MSL0DT5) CAN0 Message Slot 0 Data 7 (C0MSL0DT7) CAN0 Message Slot 0 Time Stamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) CAN0 Message Slot 1 Data 0 (C0MSL1DT0) CAN0 Message Slot 1 Data 2 (C0MSL1DT2) CAN0 Message Slot 1 Data 4 (C0MSL1DT4) CAN0 Message Slot 1 Data 6 (C0MSL1DT6) CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) CAN0 Message Slot 1 Data 1 (C0MSL1DT1) CAN0 Message Slot 1 Data 3 (C0MSL1DT3) CAN0 Message Slot 1 Data 5 (C0MSL1DT5) CAN0 Message Slot 1 Data 7 (C0MSL1DT7) CAN0 Message Slot 1 Time Stamp (C0MSL1TSP) CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) CAN0 Message Slot 2 Data 0 (C0MSL2DT0) CAN0 Message Slot 2 Data 2 (C0MSL2DT2) CAN0 Message Slot 2 Data 4 (C0MSL2DT4) CAN0 Message Slot 2 Data 6 (C0MSL2DT6) CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) CAN0 Message Slot 2 Data 1 (C0MSL2DT1) CAN0 Message Slot 2 Data 3 (C0MSL2DT3) CAN0 Message Slot 2 Data 5 (C0MSL2DT5) CAN0 Message Slot 2 Data 7 (C0MSL2DT7) CAN0 Message Slot 2 Time Stamp (C0MSL2TSP) CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) CAN0 Message Slot 3 Data 0 (C0MSL3DT0) CAN0 Message Slot 3 Data 2 (C0MSL3DT2) CAN0 Message Slot 3 Data 4 (C0MSL3DT4) CAN0 Message Slot 3 Data 6 (C0MSL3DT6) CAN0 Message Slot 3 Data 1 (C0MSL3DT1) CAN0 Message Slot 3 Data 3 (C0MSL3DT3) CAN0 Message Slot 3 Data 5 (C0MSL3DT5) CAN0 Message Slot 3 Data 7 (C0MSL3DT7) CAN0 Message Slot 3 Time Stamp (C0MSL3TSP) CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0) CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0) CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2) CAN0 Message Slot 4 Data 0 (C0MSL4DT0) CAN0 Message Slot 4 Data 2 (C0MSL4DT2) CAN0 Message Slot 4 Data 4 (C0MSL4DT4) CAN0 Message Slot 4 Data 6 (C0MSL4DT6) CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1) CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1) CAN0 Message Slot 4 Data Length Register (C0MSL4DLC) CAN0 Message Slot 4 Data 1 (C0MSL4DT1) CAN0 Message Slot 4 Data 3 (C0MSL4DT3) CAN0 Message Slot 4 Data 5 (C0MSL4DT5) CAN0 Message Slot 4 Data 7 (C0MSL4DT7) CAN0 Message Slot 4 Time Stamp (C0MSL4TSP) CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0) CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0) CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1) CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1) Blank addresses are reserved areas. Figure 3.4.12 Register Mapping of the SFR Area (10) 3-20 32171 Group User's Manual (Rev.2.00) 3 Addres s D0 H'0080 1154 H'0080 1156 H'0080 1158 H'0080 115A H'0080 115C H'0080 115E H'0080 1160 H'0080 1162 H'0080 1164 H'0080 1166 H'0080 1168 H'0080 116A H'0080 116C H'0080 116E H'0080 1170 H'0080 1172 H'0080 1174 H'0080 1176 H'0080 1178 H'0080 117A H'0080 117C H'0080 117E H'0080 1180 H'0080 1182 H'0080 1184 H'0080 1186 H'0080 1188 H'0080 118A H'0080 118C H'0080 118E H'0080 1190 H'0080 1192 H'0080 1194 H'0080 1196 H'0080 1198 H'0080 119A H'0080 119C H'0080 119E H'0080 11A0 H'0080 11A2 H'0080 11A4 H'0080 11A6 +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) CAN0 Message Slot 5 Data 0 (C0MSL5DT0) CAN0 Message Slot 5 Data 2 (C0MSL5DT2) CAN0 Message Slot 5 Data 4 (C0MSL5DT4) CAN0 Message Slot 5 Data 6 (C0MSL5DT6) CAN0 Message Slot 5 Data Length Register (C0MSL5DLC) CAN0 Message Slot 5 Data 1 (C0MSL5DT1) CAN0 Message Slot 5 Data 3 (C0MSL5DT3) CAN0 Message Slot 5 Data 5 (C0MSL5DT5) CAN0 Message Slot 5 Data 7 (C0MSL5DT7) CAN0 Message Slot 5 Time Stamp (C0MSL5TSP) CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0) CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0) CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2) CAN0 Message Slot 6 Data 0 (C0MSL6DT0) CAN0 Message Slot 6 Data 2 (C0MSL6DT2) CAN0 Message Slot 6 Data 4 (C0MSL6DT4) CAN0 Message Slot 6 Data 6 (C0MSL6DT6) CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1) CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1) CAN0 Message Slot 6 Data Length Register (C0MSL6DLC) CAN0 Message Slot 6 Data 1 (C0MSL6DT1) CAN0 Message Slot 6 Data 3 (C0MSL6DT3) CAN0 Message Slot 6 Data 5 (C0MSL6DT5) CAN0 Message Slot 6 Data 7 (C0MSL6DT7) CAN0 Message Slot 6 Time Stamp (C0MSL6TSP) CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0) CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0) CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2) CAN0 Message Slot 7 Data 0 (C0MSL7DT0) CAN0 Message Slot 7 Data 2 (C0MSL7DT2) CAN0 Message Slot 7 Data 4 (C0MSL7DT4) CAN0 Message Slot 7 Data 6 (C0MSL7DT6) CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1) CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1) CAN0 Message Slot 7 Data Length Register (C0MSL7DLC) CAN0 Message Slot 7 Data 1 (C0MSL7DT1) CAN0 Message Slot 7 Data 3 (C0MSL7DT3) CAN0 Message Slot 7 Data 5 (C0MSL7DT5) CAN0 Message Slot 7 Data 7 (C0MSL7DT7) CAN0 Message Slot 7 Time Stamp (C0MSL7TSP) CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0) CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0) CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2) CAN0 Message Slot 8 Data 0 (C0MSL8DT0) CAN0 Message Slot 8 Data 2 (C0MSL8DT2) CAN0 Message Slot 8 Data 4 (C0MSL8DT4) CAN0 Message Slot 8 Data 6 (C0MSL8DT6) CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1) CAN0 Message Slot 8 Extended ID1 (C0MSL8EID1) CAN0 Message Slot 8 Data Length Register (C0MSL8DLC) CAN0 Message Slot 8 Data 1 (C0MSL8DT1) CAN0 Message Slot 8 Data 3 (C0MSL8DT3) CAN0 Message Slot 8 Data 5 (C0MSL8DT5) CAN0 Message Slot 8 Data 7 (C0MSL8DT7) CAN0 Message Slot 8 Time Stamp (C0MSL8TSP) CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0) CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0) CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2) CAN0 Message Slot 9 Data 0 (C0MSL9DT0) CAN0 Message Slot 9 Data 2 (C0MSL9DT2) CAN0 Message Slot 9 Data 4 (C0MSL9DT4) CAN0 Message Slot 9 Data 6 (C0MSL9DT6) CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1) CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1) CAN0 Message Slot 9 Data Length Register (C0MSL9DLC) CAN0 Message Slot 9 Data 1 (C0MSL9DT1) CAN0 Message Slot 9 Data 3 (C0MSL9DT3) CAN0 Message Slot 9 Data 5 (C0MSL9DT5) CAN0 Message Slot 9 Data 7 (C0MSL9DT7) CAN0 Message Slot 9 Time Stamp (C0MSL9TSP) CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0) CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0) CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1) CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1) CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2) CAN0 Message Slot 10 Data Length Register (C0MSL10DLC) CAN0 Message Slot 10 Data 0 (C0MSL10DT0) CAN0 Message Slot 10 Data 1 (C0MSL10DT1) Blank addresses are reserved areas. . Figure 3.4.13 Register Mapping of the SFR Area (11) 3-21 32171 Group User's Manual (Rev.2.00) 3 Addres s D0 H'0080 11A8 H'0080 11AA H'0080 11AC H'0080 11AE H'0080 11B0 H'0080 11B2 H'0080 11B4 H'0080 11B6 H'0080 11B8 H'0080 11BA H'0080 11BC H'0080 11BE H'0080 11C0 H'0080 11C2 H'0080 11C4 H'0080 11C6 H'0080 11C8 H'0080 11CA H'0080 11CC H'0080 11CE H'0080 11D0 H'0080 11D2 H'0080 11D4 H'0080 11D6 H'0080 11D8 H'0080 11DA H'0080 11DC H'0080 11DE H'0080 11E0 H'0080 11E2 H'0080 11E4 H'0080 11E6 H'0080 11E8 H'0080 11EA H'0080 11EC H'0080 11EE H'0080 11F0 H'0080 11F2 H'0080 11F4 H'0080 11F6 H'0080 11F8 H'0080 11FA H'0080 11FC H'0080 11FE ~ ~ H'0080 3FFE Blank addresses are reserved areas. . CAN0 Message Slot 10 Data 2 (C0MSL10DT2) CAN0 Message Slot 10 Data 4 (C0MSL10DT4) CAN0 Message Slot 10 Data 6 (C0MSL10DT6) +0 Address D7 D8 ADDRESS SPACE 3.4 Internal RAM/SFR Areas +1 Address D15 CAN0 Message Slot 10 Data 3 (C0MSL10DT3) CAN0 Message Slot 10 Data 5 (C0MSL10DT5) CAN0 Message Slot 10 Data 7 (C0MSL10DT7) CAN0 Message Slot 10 Time Stamp (C0MSL10TSP) CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0) CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0) CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1) CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1) CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2) CAN0 Message Slot 11 Data Length Register (C0MSL11DLC) CAN0 Message Slot 11 Data 0 (C0MSL11DT0) CAN0 Message Slot 11 Data 2 (C0MSL11DT2) CAN0 Message Slot 11 Data 4 (C0MSL11DT4) CAN0 Message Slot 11 Data 6 (C0MSL11DT6) CAN0 Message Slot 11 Data 1 (C0MSL11DT1) CAN0 Message Slot 11 Data 3 (C0MSL11DT3) CAN0 Message Slot 11 Data 5 (C0MSL11DT5) CAN0 Message Slot 11 Data 7 (C0MSL11DT7) CAN0 Message Slot 11 Time Stamp (C0MSL11TSP) CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0) CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0) CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2) CAN0 Message Slot 12 Data 0 (C0MSL12DT0) CAN0 Message Slot 12 Data 2 (C0MSL12DT2) CAN0 Message Slot 12 Data 4 (C0MSL12DT4) CAN0 Message Slot 12 Data 6 (C0MSL12DT6) CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1) CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1) CAN0 Message Slot 12 Data Length Register (C0MSL12DLC) CAN0 Message Slot 12 Data 1 (C0MSL12DT1) CAN0 Message Slot 12 Data 3 (C0MSL12DT3) CAN0 Message Slot 12 Data 5 (C0MSL12DT5) CAN0 Message Slot 12 Data 7 (C0MSL12DT7) CAN0 Message Slot 12 Time Stamp (C0MSL12TSP) CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0) CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0) CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1) CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1) CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2) CAN0 Message Slot 13 Data Length Register (C0MSL13DLC) CAN0 Message Slot 13 Data 0 (C0MSL13DT0) CAN0 Message Slot 13 Data 2 (C0MSL13DT2) CAN0 Message Slot 13 Data 4 (C0MSL13DT4) CAN0 Message Slot 13 Data 6 (C0MSL13DT6) CAN0 Message Slot 13 Data 1 (C0MSL13DT1) CAN0 Message Slot 13 Data 3 (C0MSL13DT3) CAN0 Message Slot 13 Data 5 (C0MSL13DT5) CAN0 Message Slot 13 Data 7 (C0MSL13DT7) CAN0 Message Slot 13 Time Stamp (C0MSL13TSP) CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0 CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0) CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1) CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1) CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2) CAN0 Message Slot 14 Data Length Register (C0MSL14DLC) CAN0 Message Slot 14 Data 0 (C0MSL14DT0) CAN0 Message Slot 14 Data 2 (C0MSL14DT2) CAN0 Message Slot 14 Data 4 (C0MSL14DT4) CAN0 Message Slot 14 Data 6 (C0MSL14DT6) CAN0 Message Slot 14 Data 1 (C0MSL14DT1) CAN0 Message Slot 14 Data 3 (C0MSL14DT3) CAN0 Message Slot 14 Data 5 (C0MSL14DT5) CAN0 Message Slot 14 Data 7 (C0MSL14DT7) CAN0 Message Slot 14 Time Stamp (C0MSL14TSP) CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0) CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0) CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1) CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1) CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2) CAN0 Message Slot 15 Data Length Register (C0MSL15DLC) CAN0 Message Slot 15 Data 0 (C0MSL15DT0) CAN0 Message Slot 15 Data 2 (C0MSL15DT2) CAN0 Message Slot 15 Data 4 (C0MSL15DT4) CAN0 Message Slot 15 Data 6 (C0MSL15DT6) CAN0 Message Slot 15 Data 1 (C0MSL15DT1) CAN0 Message Slot 15 Data 3 (C0MSL15DT3) CAN0 Message Slot 15 Data 5 (C0MSL15DT5) CAN0 Message Slot 15 Data 7 (C0MSL15DT7) CAN0 Message Slot 15 Time Stamp (C0MSL11TSP) ~ ~ Figure 3.4.14 Register Mapping of the SFR Area (12) 3-22 32171 Group User's Manual (Rev.2.00) 3 3.5 EIT Vector Entry ADDRESS SPACE 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/external extension areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch instructions and not the jump addresses that are written here. For details, refer to Chapter 4, "EIT." 0 3 1 H'0000 0000 H'0000 0004 RI (Reset Interrupt) H'0000 0008 H'0000 000C H'0000 0010 H'0000 0014 SBI (System Break Interrupt) H'0000 0018 H'0000 001C H'0000 0020 H'0000 0024 H'0000 0028 H'0000 002C H'0000 0030 H'0000 0034 H'0000 0038 H'0000 003C H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 EI (External Interrupt) (Note 1) AE (Address Exception) RIE (Reserved Instruction Exception) ~ ~ Note 1: When flash entry bit = 1 (i.e., flash enable mode), the EI vector entry is at H'0080 4000. Figure 3.5.1 EIT Vector Entry 3-23 32171 Group User's Manual (Rev.2.00) 3 3.6 ICU Vector Table ADDRESS SPACE 3.6 ICU Vector Table The ICU vector table is used by the internal interrupt controller. The start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set at the addresses shown below. For details, refer to Chapter 5, "Interrupt Controller." The 32171's ICU vector table is shown in Figures 3.6.1 and 3.6.2. Address D0 +0 Address D7 D8 +1 Address D15 H'0000 0094 H'0000 0096 H'0000 0098 H'0000 009A H'0000 009C H'0000 009E H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 MJT Input Interrupt 4 Handler Start Address (A0-A15) MJT Input Interrupt 4 Handler Start Address (A16-A31) MJT Input Interrupt 3 Handler Start Address (A0-A15) MJT Input Interrupt 3 Handler Start Address (A16-A31) MJT Input Interrupt 2 Handler Start Address (A0-A15) MJT Input Interrupt 2 Handler Start Address (A16-A31) MJT Input Interrupt 1 Handler Start Address (A0-A15) MJT Input Interrupt 1 Handler Start Address (A16-A31) MJT Output Interrupt 7 Handler Start Address (A0-A15) MJT Output Interrupt 7 Handler Start Address (A16-A31) MJT Output Interrupt 6 Handler Start Address (A0-A15) MJT Output Interrupt 6 Handler Start Address (A16-A31) MJT Output Interrupt 5 Handler Start Address (A0-A15) MJT Output Interrupt 5 Handler Start Address (A16-A31) MJT Output Interrupt 4 Handler Start Address (A0-A15) MJT Output Interrupt 4 Handler Start Address (A16-A31) MJT Output Interrupt 3 Handler Start Address (A0-A15) MJT Output Interrupt 3 Handler Start Address (A16-A31) MJT Output Interrupt 2 Handler Start Address (A0-A15) MJT Output Interrupt 2 Handler Start Address (A16-A31) MJT Output Interrupt 1 Handler Start Address (A0-A15) MJT Output Interrupt 1 Handler Start Address (A16-A31) MJT Output Interrupt 0 Handler Start Address (A0-A15) MJT Output Interrupt 0 Handler Start Address (A16-A31) ~ Blank addresses are reserved areas. Figure 3.6.1 ICU Vector Table of the 32171 (1/2) ~ 3-24 32171 Group User's Manual (Rev.2.00) 3 Address D0 +0 Address D7 D8 +1 Address ADDRESS SPACE 3.6 ICU Vector Table D15 H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C H'0000 010E DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address (A16-A31) SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address (A16-A31) A-D0 Conversion Interrupt Handler Start Address (A0-A15) A-D0 Conversion Interrupt Handler Start Address (A16-A31) DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A0-A15) SIO2,3 Transmit/Receive Interrupt Handler Start Address (A16-A31) RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) Blank addresses are reserved areas. Figure 3.6.2 ICU Vector Table of the 32171 (2/2) 3-25 32171 Group User's Manual (Rev.2.00) 3 3.7 Notes on Address Space * Virtual flash emulation function ADDRESS SPACE 3.7 Notes on Address Space The 32171 can map one 8-Kbyte block of internal RAM beginning with the start address into one of 8-Kbyte areas (L banks) of the internal flash memory and can map up to two 4-Kbyte blocks of internal RAM beginning with address H'0080 6000 into one of 4-Kbyte areas (S banks) of the internal flash memory. This capability is referred to as the "virtual-flash emulation" function. For details about this function, refer to Section 6.7, "Virtual-Flash Emulation Function." 3-26 32171 Group User's Manual (Rev.2.00) CHAPTER 4 EIT 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Outline of EIT EIT Events EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing Trap Processing EIT Priority Levels Example of EIT Processing Precautions on EIT 4 4.1 Outline of EIT EIT 4.1 Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt, and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. In the M32R/ECU, this type of event includes Address Exception (AE) and Reserved Instruction Exception (RIE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated in hardware by a signal from an external source. In the M32R/ECU, this type of event includes External Interrupt (EI), System Break Interrupt (SBI), and Reset Interrupt (RI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS's system call by the programmer. EIT Exception Reserved Instruction Exception (RIE) Address Exception (AE) Interrupt Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap TRAP Figure 4.1.1 Classification of EITs 4-2 32171 Group User's Manual (Rev.2.00) 4 4.2 EIT Events 4.2.1 Exception (1) Reserved Instruction Exception (RIE) EIT 4.2 EIT Events Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions. 4.2.2 Interrupt (1) Reset Interrupt (RI) ____________ Reset Interrupt (RI) is always accepted by entering the RESET signal. The reset interrupt is assigned the highest priority. (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The 32171's internal interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. 4.2.3 Trap Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0-15. 4-3 32171 Group User's Manual (Rev.2.00) 4 4.3 EIT Processing Procedure EIT 4.3 EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below. EIT request generated Program execution restarted Instruction Instruction Instruction A B C Program suspended EIT request accepted Instruction Instruction **** C D Instruction processingcanceled type (RIE, AE) Instruction processing -completed type (EI, TRAP) PC BPC Hardware PSW (B)PSW preprocessing Hardware postprocessing (B)PSW PSW BPC PC User-created EIT handler EIT vector entry Branch instruc -tion EIT handlers except for SBI BPC, (B)PSW, and general-purpose registers saved to stack Processing by handler General-purpose registers, (B)PSW and BPC restored from stack RTE instruction (SBI) SBI (System Break Interrupt processing) Program terminated or system is reset Note: (B)PSW denotes the BPSW field of the PSW register. Figure 4.3.1 Outline of EIT Processing Procedure 4-4 32171 Group User's Manual (Rev.2.00) 4 EIT 4.3 EIT Processing Procedure When an EIT is accepted, the M32R/ECU saves the PC and PSW (as will be described later) and branches to the EIT vector. The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction (note that these are not branch address) for the EIT handler is written. In the M32R/ECU's hardware preprocessing, only the contents of the PC and PSW registers are transferred to the backup registers (BPC register and the BPSW field of the PSW register), and no other operations are performed. Therefore, please make sure the BPC register, the PSW register (including the BPSW field), and the general-purpose registers to be used in the EIT handler are saved to the stack by the EIT handler you write. (Remember that these registers must be saved to the stack in a program by the user.) When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the "RTE" instruction. Control is thereby returned from EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the M32R/ECU's hardware postprocessing, the contents of the backup registers (BPC register and the BPSW field of the PSW register) are moved back to the PC and PSW registers. 4-5 32171 Group User's Manual (Rev.2.00) 4 4.4 EIT Processing Mechanism EIT 4.4 EIT Processing Mechanism The M32R/ECU's EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (BPC register and the BPSW field of the PSW register). The M32R/ECU's internal EIT processing mechanism is shown below. M32R/ECU M32R CPU core High RI RESET RI AE, RIE, TRAP Priority SBI SBI SBI Internal peripheral I/O * * * * * * Interrupt controller (ICU) EI EI Low IE flag (PSW) BPC register BPSW PSW PSW register PC register Figure 4.4.1 The M32R/ECU's EIT Processing Mechanism 4-6 32171 Group User's Manual (Rev.2.00) 4 4.5 Acceptance of EIT Events EIT 4.5 Acceptance of EIT Events When an EIT event occurs, the M32R/ECU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events EIT Event Reserved Instruction Exception (RIE) Address Exception (AE) Type of Processing Instruction processingcanceled type Instruction processingcanceled type Reset Interrupt (RI) Instruction processingaborted type System Break Interrupt (SBI) External Interrupt (EI) Instruction processingcompleted type Instruction processingcompleted type Trap (TRAP) Instruction processingcompleted type Break in instructions (only word boundaries) Break in instructions (only word boundaries) Break in instructions PC value of TRAP instruction + 4 PC value of the next instruction PC value of the next instruction Acceptance Timing During instruction execution During instruction execution Each machine cycle Values Set in BPC Register PC value of the instruction which generated RIE PC value of the instruction which generated AE Indeterminate value 4-7 32171 Group User's Manual (Rev.2.00) 4 EIT 4.6 Saving and Restoring the PC and PSW 4.6 Saving and Restoring the PC and PSW The following describes operation of the M32R at the time when it accepts an EIT and when it executes the "RTE" instruction. (1) Hardware preprocessing when an EIT is accepted (a) Save the SM, IE, and C bits of the PSW register BSM BIE BC SM IE C Remains unchanged (RIE, AE, TRAP) or set to 0 (SBI, EI, RI) Set to 0 Set to 0 (b) Update the SM, IE, and C bits of the PSW register SM IE C (c) Save the PC register BPC PC (d) Set the vector address in the PC register Branches to the EIT vector and executes the branch instruction ("BRA" instruction) written in it, thereby transferring control to the user-created EIT handler. (2) Hardware postprocessing when the "RTE" instruction is executed (e) Restore the SM, IE, and C bits of the PSW register from their backup bits. SM BSM IE C BIE BC (f) Restore the value of the PC register from the BPC register PC BPC Note: * The value of the BPC register and those of the BSM, BIE, and BC bits of the PSW register after execution of the "RTE" instruction are indeterminate. 4-8 32171 Group User's Manual (Rev.2.00) 4 (a) Save SM, IE, and C bits BSM BIE BC SM IE C EIT 4.6 Saving and Restoring the PC and PSW (c) Save PC BPC PC (d) Set vector address in PC PC Vector address (b) Update SM, IE, and C bits SM IE C Unchanged/0 0 0 (e) Restore BSM, BIE, and BC bits from backup bits SM IE C BSM BIE BC (f) Restore PC value from BPC The value of BPC after execution of the "RTE" instruction is indeterminate. The values of BSM, BIE, and BC bits after execution of the "RTE" instruction are indeterminate. PSW BPC PC When EIT is accepted (a) (b) (c) (d) When "RTE" instruction is executed (e) (f) BPSW field 0(MSB) 7 8 15 16 17 23 24 25 PSW field 31(LSB) PSW 0000000000000000 00000 00000 BSM BIE BC SM IE C Figure 4.6.1 Saving and Restoring the PC and PSW 4-9 32171 Group User's Manual (Rev.2.00) 4 4.7 EIT Vector Entry EIT 4.7 EIT Vector Entry The EIT vector entry is located in the user space starting from address H'0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Reset Interrupt Abbreviation Vector Address RI H'0000 0000 (Note 1) H'0000 0010 H'0000 0020 SM 0 0 Indeterminate IE 0 0 0 BPC Indeterminate PC of the next instruction PC of the instruction that generated EIT AE H'0000 0030 Indeterminate 0 PC of the instruction that generated RIE Trap TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 External Interrupt EI H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of the next instruction System Break Interrupt SBI Reserved Instruction Exception Address Exception RIE H'0000 0080 (Note 2) Note 1: During boot mode, this vector address is moved to the beginning of the boot ROM (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H'0080 4000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." 4-10 32171 Group User's Manual (Rev.2.00) 4 4.8 Exception Processing 4.8.1 Reserved Instruction Exception (RIE) [Occurrence Conditions] EIT 4.8 Exception Processing Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction which generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits - the BSM, BIE, and BC bits. BSM BIE BC SM IE C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM Unchanged BIE BC (3) Saving PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the "RTE" instruction returns after completion of processing by the EIT handler is address 4. (This is because the two low-order bits are cleared to "00" when returning to the PC.) 0 0 4-11 32171 Group User's Manual (Rev.2.00) 4 EIT 4.8 Exception Processing +0 Address Return address H'00 H'04 H'08 H'0C +1 +2 +3 +0 +1 +2 +3 ~ RIE occurred ~ Return address Address H'00 H'04 H'08 H'0C ~ ~ RIE occurred ~ BPC H'04 ~ ~ BPC H'06 ~ Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0020 in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0020 of the EIT vector entry by the user to jump to the start address of the user-created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. 4-12 32171 Group User's Manual (Rev.2.00) 4 4.8.2 Address Exception (AE) [Occurrence Conditions] EIT 4.8 Exception Processing Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur: * When the LDH, LDUH, or STH instruction accesssed an address whose two low-order bits are "01" or "11" * When the LD, ST, LOCK, or UNLOCK instruction accessed an address whose two low-order bits are "01," "10," or "11" When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits - the BSM, BIE, and BC bits. BSM BIE BC SM IE C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM Unchanged IE C (3) Saving PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the address exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the "RTE" instruction returns after completion of processing by the EIT handler is address 4. (This is because the two low-order bits are cleared to "00" when returning to the PC.) 0 0 4-13 32171 Group User's Manual (Rev.2.00) 4 EIT 4.8 Exception Processing +0 Address H'00 Return address H'04 H'08 H'0C +1 +2 +3 +0 +1 +2 +3 ~ AE occurred ~ Return address Address H'00 H'04 H'08 H'0C ~ ~ AE occurred ~ BPC H'04 ~ ~ BPC H'06 ~ Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0030 in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0030 of the EIT vector entry by the user to jump to the start address of the user-created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. 4-14 32171 Group User's Manual (Rev.2.00) 4 4.9 Interrupt Processing 4.9.1 Reset Interrupt (RI) [Occurrence Conditions] EIT 4.9 Interrupt Processing ____________ Reset Interrupt (RI) is unconditionally accepted in any machine cycle by pulling the RESET input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE, and C bits The SM, IE, and C bits of the PSW register are initialized in the manner shown below. SM IE C 0 0 0 For the reset interrupt, the values of BSM, BIE, and BC bits are indeterminate. (2) Branching to the EIT vector entry Control branches to the address H'0000 0000 in the user space. However, when operating in boot mode, control goes to the beginning of the boot ROM (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." (3) Jumping from the EIT vector entry to the user program The M32R/ECU executes the instruction written at address H'0000 0000 of the EIT vector entry by the user. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the program you created. 4-15 32171 Group User's Manual (Rev.2.00) 4 4.9.2 System Break Interrupt (SBI) EIT 4.9 Interrupt Processing System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when some fatal event has already occurred to the system when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] _______ A system break interrupt is accepted by a falling edge on SBI input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt may be accepted immediately after branching.) Order in which instructions are executed Address 1000 Address 1002 Address 1004 32-bit instruction Address 1008 16-bit instruction 16-bit instruction Interrupt may be accepted Interrupt cannot be accepted Interrupt may be accepted Interrupt may be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted 4-16 32171 Group User's Manual (Rev.2.00) 4 [EIT Processing] (1) Saving SM, IE, and C bits EIT 4.9 Interrupt Processing The SM, IE, and C bits of the PSW register are saved to their backup bits-the BSM, BIE, and BC bits. BSM BIE BC SM IE C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM IE C (3) Saving PC The content (always word boundary) of the PC register is saved to the BPC register. (4) Branching to the EIT vector entry Control branches to the address H'0000 0010 in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0010 of the EIT vector entry by the user to jump to the start address of the user-created handler. The system break interrupt can only be used when some fatal event has occurred to the system. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. 0 0 0 4-17 32171 Group User's Manual (Rev.2.00) 4 4.9.3 External Interrupt (EI) EIT 4.9 Interrupt Processing An external interrupt is generated upon an interrupt request which is output by the 32171's internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, refer to Chapter 5, "Interrupt Controller." For details about the interrupt sources, refer to each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the 32171's internal interrupt controller. These interrupt requests are notified to the M32R CPU by the interrupt controller. The M32R/ECU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = 1, accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt may be accepted immediately after branching.) Order in which instructions are executed Address 1000 Address 1002 Address 1004 32-bit instruction Address 1008 16-bit instruction 16-bit instruction Interrupt may be accepted Interrupt cannot be accepted Interrupt may be accepted Interrupt may be accepted Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted 4-18 32171 Group User's Manual (Rev.2.00) 4 [EIT Processing] (1) Saving SM, IE, and C bits EIT 4.9 Interrupt Processing The SM, IE, and C bits of the PSW register are saved to their backup bits - the BSM, BIE, and BC bits. BSM BIE BC SM IE C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM IE C (3) Saving PC The content (always word boundary) of the PC register is saved to the BPC register. (4) Branching to the EIT vector entry Control branches to the address H'0000 0080 in the user space. However, when operating in flash E/W enable mode, control goes to the beginning of the internal RAM (address H'0080 4000). (For details, refer to Section 6.5, "Writing to Internal Flash Memory.") This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at address H'0000 0080 of the EIT vector entry by the user to jump to the start address of the user-created handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. 0 0 0 4-19 32171 Group User's Manual (Rev.2.00) 4 4.10 Trap Processing 4.10.1 Trap (TRAP) [Occurrence Conditions] EIT 4.10 Trap Processing Traps refer to software interrupts which are generated by executing the "TRAP" instruction. Sixteen distinct traps are generated, each corresponding to one of "TRAP" instruction operands 0-15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits - the BSM, BIE, and BC bits. BSM BIE BC SM IE C (2) Updating SM, IE, and C bits The SM, IE, and C bits of the PSW register are updated as shown below. SM IE C (3) Saving PC When the trap instruction is executed, the "PC value of the TRAP instruction + 4" is set in the BPC register. For example, if the "TRAP" instruction is located at address 4, the value H'08 is set in the BPC register. Similarly, if the instruction is located at address 6, the value H'0A is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30] = 1). However, in either case of the above, the address to which the "RTE" instruction returns after completion of processing by the EIT handler is address 8. (This is because the two low-order bits are cleared to "00" when returning to the PC.) Unchanged 0 0 4-20 32171 Group User's Manual (Rev.2.00) 4 EIT 4.10 Trap Processing +0 Address +1 +2 +3 +0 +1 +2 +3 ~ TRAP occurred ~ Return address Address ~ ~ TRAP occurred Return address H'00 H'04 H'08 H'0C H'00 H'04 H'08 H'0C ~ BPC ~ H'08 ~ BPC ~ H'0A Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to the addresses H'0000 0040 through H'0000 007C in the user space. This is the last operation performed in hardware preprocessing by the M32R/ECU. (5) Jumping from the EIT vector entry to the user-created handler The M32R/ECU executes the "BRA" instruction written at addresses H'0000 0040 through H'0000 007C of the EIT vector entry by the user to jump to the start address of the usercreated handler. At the beginning of the EIT handler you created, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and then execute the "RTE" instruction. As you execute the "RTE" instruction, hardware postprocessing is automatically performed by the M32R/ECU. 4-21 32171 Group User's Manual (Rev.2.00) 4 4.11 EIT Priority Levels EIT 4.11 EIT Priority Levels The table below lists the priority levels of EIT events. When multiple EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT Priority 1(Highest) EIT Event Reset Interrupt (RI) Type of Processing Values Set in BPC Register Instruction processing Indeterminate -aborted type Address Exception (AE) Instruction processing- PC of the instruction that canceled type generated AE 2 Reserved Instruction Exception (RIE) Trap (TRAP) Instruction processing- PC of the instruction that canceled type generated AE Instruction processing- TRAP instruction + 4 completed type 3 System Break Interrupt (SBI) Instruction processing- PC of the next instruction completed type Instruction processing- PC of the next instruction completed type 4 External Interrupt (EI) Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the 32171's internal interrupt controller. For details, refer to Chapter 5, "Interrupt Controller." 4-22 32171 Group User's Manual (Rev.2.00) 4 4.12 Example of EIT Processing (1) When RIE, AE, SBI, EI, or TRAP occurs singly EIT 4.12 Example of EIT Processing IE=1 BPC register = Return address A IE=0 RIE, AE, SBI, EI, or TRAP occurrs Singly Return address A: If IE = 0, no events but reset and SBI are accepted IE=1 RTE instruction :EIT handler Figure 4.12.1 Processing of Events When RIE, AE, SBI, EI, or TRAP Occurs Singly (2) When RIE, AE, or TRAP and EI occurs simultaneously IE=1 IE=0 RIE, AE, or TRAP and EI occurs simultaneously IE=1 IE=0 Return address A: IE=1 RIE, AE, or TRAP is accepted first BPC register = Return address A RTE instruction EI is accepted next BPC register = Return address A RTE instruction :EIT handler Figure 4.12.2 Processing of Events when RIE, AE, or TRAP and EI Occurs Simultaneously 4-23 32171 Group User's Manual (Rev.2.00) 4 EIT 4.12 Example of EIT Processing EIT vector entry ~ BRA instruction ~ ~ EIT handler (Any event other than SBI) (SBI) ~ PC BPC Hardware preprocessing PSW (B)PSW Save BPC to stack Save PSW to stack Save general-purpose registers to stack System Break Interrupt processing Program being executed * * * * * * * * * * * * * * EIT event occurs Program terminated or system reset Processing by EIT handler Restore generalpurpose registers Restore PSW Restore BPC (B)PSW PSW Hardware BPC PC postprocessing RTE Figure 4.12.3 Example of EIT Processing 4-24 32171 Group User's Manual (Rev.2.00) 4 4.13 Precautions on EIT EIT 4.13 Precautions on EIT Address Exception requires caution because when an address exception occurs pursuant to execution of an instruction (one of the following three) that uses the "register indirect + register update" addressing mode, the value of the automatically updated register (Rsrc or Rsrc2) becomes indeterminate. Except that the values of Rsrc and Rsrc2 are indeterminate, the behavior is the same as when using other addressing modes. * Applicable instructions LD ST ST Rdest, @Rsrc+ Rsrc1, @-Rsrc2 Rsrc1, @+Rsrc2 If the above applies, because the register value becomes indeterminate as explained, consideration must be taken before continuing with system processing. (If an address exception occurs, it means that some fatal fault already occurred in the system at that point in time. Therefore, use EIT on condition that after processing by the address exception handler, the CPU will not return to the program it was executing when the exception occurred.) 4-25 32171 Group User's Manual (Rev.2.00) 4 EIT 4.13 Precautions on EIT * This is a blank page. * 4-26 32171 Group User's Manual (Rev.2.00) CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.2 ICU Related Registers 5.3 Interrupt Request Sources in Internal Peripheral I/O 5.4 ICU Vector Table 5.5 Description of Interrupt Operation 5.6 Description of System Break Interrupt (SBI) Operation 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.1 Outline of the Interrupt Controller (ICU) The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as external interrupts (EI). There are a total of 22 interrupt sources for the maskable interrupts from internal peripheral I/Os, which are managed by assigning them one of eight priority levels including an interrupt-disabled state. When multiple interrupt requests of the same priority level occur simultaneously, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is an interrupt request generated by a falling _______ edge on the SBI signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. When the ICU has finished servicing an SBI, terminate or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the interrupt controller are outlined in the table below. Table 5.1.1 Outline of Interrupt Controller (ICU) Item Interrupt source Specification Maskable interrupt from internal peripheral I/O : 22 sources (Note 1) _______ System break interrupt Level management : 1 source (entered from SBI pin) Eight levels including an interrupt-disabled state (However, interrupts of the same level have their priorities resolved by fixed hardware priority.) Note 1: This is the number of interrupt requests divided into groups. There are actually a total of 70 interrupt request sources when counted individually. 5-2 32171 Group User's Manual (Rev.2.00) 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) Interrupt controller System Break Interrupt request generated (nonmaskable) SBI Control Register SBIREQ (SBICR) SBI SBI To the CPU core Peripheral circuits Priority resolution by fixed hardware priority Edgerecognized Edgerecognized IREQ IREQ IREQ Priority resolution by interrupt priority levels set Interrupt request Interrupt request Interrupt request Edgerecognized ILEVEL Maskable interrupt request generated (maskable) . . . . . . . . . . . . . . Levelrecognized Levelrecognized Levelrecognized Interrupt Vector Register (IVECT) IMASK Compared EI NEW_IMASK IREQ IREQ IREQ To the CPU core Interrupt control circuit Interrupt control circuit Interrupt control circuit Interrupt Mask Register (IMASK) . . Interrupt Control Register Figure 5.1.1 Block Diagram of the Interrupt Controller 5-3 32171 Group User's Manual (Rev.2.00) 5 5.2 ICU Related Registers INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers The diagram below shows a register map associated with the Interrupt Controller (ICU). Address D0 +0 Address D7 D8 +1 Address D15 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 Interrupt Vector Register (IVECT) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) ~ ~ ~ ~ H'0080 0060 H'0080 0062 H'0080 0064 H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) RTD Interrupt Control Register (IRTDCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5-9 Interrupt Control Register (IDMA59CR) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) MJT Output Interrupt Control Register 0 (IMJTOCR0) MJT Output Interrupt Control Register 2 (IMJTOCR2) MJT Output Interrupt Control Register 4 (IMJTOCR4) MJT Output Interrupt Control Register 6 (IMJTOCR6) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) MJT Output Interrupt Control Register 1 (IMJTOCR1) MJT Output Interrupt Control Register 3 (IMJTOCR3) MJT Output Interrupt Control Register 5 (IMJTOCR5) MJT Output Interrupt Control Register 7 (IMJTOCR7) MJT Input Interrupt Control Register 1 (IMJTICR1) MJT Input Interrupt Control Register 2 (IMJTICR2) MJT Input Interrupt Control Register 4 (IMJTICR4) MJT Input Interrupt Control Register 3 (IMJTICR3) Blank addresses are reserved for future use. Note: The registers in the thick frames must always be accessed in halfwords. Figure 5.2.1 Interrupt Controller (ICU) Related Register Map 5-4 32171 Group User's Manual (Rev.2.00) 5 5.2.1 Interrupt Vector Register s Interrupt Vector Register (IVECT) INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 IVECT D 0 - 15 Bit Name IVECT (16 low-order bits of ICU vector table address) Function When an interrupt request is accepted, the 16 low-order bits in ICU vector table address for the accepted interrupt source is stored in this register. R W - Note: * This register must always be accessed in halfwords. (This is a read-only register). The Interrupt Vector Register (IVECT) is used when an interrupt is accepted to store the 16 loworder bits of ICU vector table address for the accepted interrupt source. Before this function can work, the ICU vector table (addresses H'0000 0094 through H'0000 010F) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16 low-order bits of ICU vector table address for the accepted interrupt request source is stored in this IVECT register. In the EIT handler, read the content of this IVECT register using "LDH" instruction to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware: (1) The interrupt priority level (ILEVEL) of the accepted interrupt request source is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.). (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). (3) The interrupt request (EI) to the CPU core is deasserted. (4) The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: * Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0") . In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register. * To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts, (The ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, therefore, does not require adding a dummy access). 5-5 32171 Group User's Manual (Rev.2.00) 5 5.2.2 Interrupt Request Mask Register s Interrupt Request Mask Register (IMASK) D0 1 2 3 4 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5 6 IMASK D7 D 0-4 5- 7 Bit Name No functions assigned IMASK (Interrupt request mask bit) 000 : Maskable interrupts are disabled 001 : Level 0 interrupts can be accepted 010 : Level 0-1 interrupts can be accepted 011 : Level 0-2 interrupts can be accepted 100 : Level 0-3 interrupts can be accepted 101 : Level 0-4 interrupts can be accepted 110 : Level 0-5 interrupts can be accepted 111 : Level 0-6 interrupts can be accepted Function R 0 W - The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt source. When the Interrupt Vector Register (IVECT) described above is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware: (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: * Do not write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0"). * To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts. 5-6 32171 Group User's Manual (Rev.2.00) 5 s SBI (System Break Interrupt) Control Register INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.3 SBI (System Break Interrupt) Control Register D0 1 2 3 4 5 6 D7 SBIREQ D 0-6 7 Bit Name No functions assigned SBI REQ (SBI request bit) 0 : SBI is not requested 1 : SBI is requested Function R 0 W - (Note 1) Note 1: This bit can only be cleared (see below). _______ The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI signal input pin. When a falling edge on the SBI signal input pin is detected and this bit is set to "1", a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0", follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Note: * Unless this bit is set to "1", do not perform the above clearing operation. 5-7 32171 Group User's Manual (Rev.2.00) 5 5.2.4 Interrupt Control Registers INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers s CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) s RTD Interrupt Control Register (IRTDCR) s SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) s DMA5-9 Interrupt Control Register (IDMA59CR) s A-D0 Converter Interrupt Control Register (IAD0CCR) s SIO0 Transmit Interrupt Control Register (ISIO0TXCR) s SIO0 Receive Interrupt Control Register (ISIO0RXCR) s SIO1 Transmit Interrupt Control Register (ISIO1TXCR) s SIO1 Receive Interrupt Control Register (ISIO1RXCR) s DMA0-4 Interrupt Control Register (IDMA04CR) s MJT Output Interrupt Control Register 0 (IMJTOCR0) s MJT Output Interrupt Control Register 1 (IMJTOCR1) s MJT Output Interrupt Control Register 2 (IMJTOCR2) s MJT Output Interrupt Control Register 3 (IMJTOCR3) s MJT Output Interrupt Control Register 4 (IMJTOCR4) s MJT Output Interrupt Control Register 5 (IMJTOCR5) s MJT Output Interrupt Control Register 6 (IMJTOCR6) s MJT Output Interrupt Control Register 7 (IMJTOCR7) s MJT Input Interrupt Control Register 1 (IMJTICR1) s MJT Input Interrupt Control Register 2 (IMJTICR2) s MJT Input Interrupt Control Register 3 (IMJTICR3) s MJT Input Interrupt Control Register 4 (IMJTICR4) 5-8 32171 Group User's Manual (Rev.2.00) 5 D0 1 9 2 10 3 11 IREQ 4 12 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5 13 6 14 ILEVEL D7 D15) (D8 D 0-2 (8-10) 3 (11) Bit Name No functions assigned IREQ Interrupt request bit Function R 0 R W - W R - 4 (12) 5-7 (13-15) No functions assigned ILEVEL Interrupt priority level bits 000 : Interrupt priority level 0 001 : Interrupt priority level 1 010 : Interrupt priority level 2 011 : Interrupt priority level 3 100 : Interrupt priority level 4 101 : Interrupt priority level 5 110 : Interrupt priority level 6 111 : Interrupt priority level 7 (Interrupt disabled) 0 R - W (1) IREQ (Interrupt Request) bit (D3 or D11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1". This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edgerecognized interrupt request generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note: * Exernal Inerrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK regiser 5-9 32171 Group User's Manual (Rev.2.00) 5 Interrupt request from each internal peripheral I/O d3 or 11 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers IREQ Set Set/clear Data bus F/F Interrupt enabled Reset IVECT read IMASK write Clear d5-7 or d13-15 3 ILEVEL (levels 0-7) Interrupt priority resolving circuit Set F/F EI To the CPU core Figure 5.2.2 Configuration of the Interrupt Control Register (Edge-recognized Type) Interrupt request from each group internal peripheral I/O Group interrupt Read Data bus d3 or 11 Read-only circuit IREQ Reset IVECT read IMASK write Interrupt enabled Clear d5-7 or d13-15 3 ILEVEL (levels 0-7) Interrupt priority resolving circuit Set F/F EI To the CPU core Figure 5.2.3 Configuration of the Interrupt Control Register (Level-recognized Type) 5-10 32171 Group User's Manual (Rev.2.00) 5 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers (2) ILEVEL (Interrupt Priority Level) (D5-D7 or D13-D15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set priority level 7 to disable interrupts from some internal peripheral I/O or priority levels 0-6 to enable interrupts. When an interrupt occurs, the interrupt controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares its priority with the IMASK value to determine whether to forward an EI request to the CPU or keep it pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set 0 (ILEVEL="000") 1 (ILEVEL="001") 2 (ILEVEL="010") 3 (ILEVEL="011") 4 (ILEVEL="100") 5 (ILEVEL="101") 6 (ILEVEL="110") 7 (ILEVEL="111") IMASK values at which interrupts are accepted Accepted when IMASK is 1-7 Accepted when IMASK is 2-7 Accepted when IMASK is 3-7 Accepted when IMASK is 4-7 Accepted when IMASK is 5-7 Accepted when IMASK is 6-7 Accepted when IMASK is 7 Not accepted (interrupts disabled) 5-11 32171 Group User's Manual (Rev.2.00) 5 INTERRUPT CONTROLLER (ICU) 5.3 Interrupt Request Sources in Internal Peripheral I/O 5.3 Interrupt Request Sources in Internal Peripheral I/O The interrupt controller receives as its inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD, and CAN. For details about these interrupts, refer to each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O Interrupt Request Sources A-D0 conversion interrupt SIO0 transmit interrupt SIO0 receive interrupt SIO1transmit interrupt SIO1 receive interrupt SIO2,3 transmit/receive interrupt RTD interrupt DMA transfer interrupt 0 DMA transfer interrupt 1 CAN0 transmit/receive & error interrupt MJT output interrupt 7 MJT output interrupt 6 MJT output interrupt 5 MJT output interrupt 4 MJT output interrupt 3 MJT output interrupt 2 MJT output interrupt 1 MJT output interrupt 0 MJT input interrupt 4 MJT input interrupt 3 MJT input interrupt 2 MJT input interrupt 1 Single-shot conversion in A-D0 converter scan mode completed, single mode completed, or comparator mode completed SIO0 transmit buffer empty interrupt SIO0 reception completed or receive error interrupt SIO1 transmit buffer empty interrupt SIO1 reception completed or receive error interrupt SIO2 reception completed or receive error interrupt, transmit buffer empty interrupt RTD interrupt generation command DMA0-4 transfer completed DMA5-9 transfer completed CAN0 transmission completed, CAN0 reception completed, CAN0 error passive, CAN0 error bus-off, CAN0 bus error MJT output interrupt group 7 (TMS0, TMS1 output) MJT output interrupt group 6 (TOP8, TOP9 output) MJT output interrupt group 5 (TOP10 output) MJT output interrupt group 4 (TIO4 - TIO7 output) MJT output interrupt group 3 (TIO8, TIO9 output) MJT output interrupt group 2 (TOP0 - TOP5 output) MJT output interrupt group 1 (TOP6, TOP7 output) MJT output interrupt group 0 (TIO0 - TIO3 output) MJT input interrupt group 4 (TIN3 input) MJT input interrupt group 3 (TIN20-TIN23 input) MJT input interrupt group 2 (TIN16-TIN19 input) MJT input interrupt group 1 (TIN0 input) Contents Number of Input Sources 1 1 1 1 1 2 1 5 5 199 ICU Type of Input Source(Note 1) Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized 2 2 1 4 2 6 2 4 1 4 4 1 Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Note 1: ICU type of input source * Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal applied to the ICU. * Level-recognized: Interrupt requests are generated when the interrupt signal applied to the ICU is held low. For these level-recognized interrupts, the ICU's Interrupt Control register IRQ bit cannot be set or cleared in software. 5-12 32171 Group User's Manual (Rev.2.00) 5 5.4 ICU Vector Table INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 22-source interrupts are assigned the following addresses: Table 5.4.1 ICU Vector Table Addresses Interrupt Source MJT Input Interrupt request 4 (TIN3 input) MJT Input Interrupt request 3 (TIN20-TIN23 input) MJT Input Interrupt request 2 (TIN16-TIN19 input) MJT Input Interrupt request 1 (TIN0 input) MJT Output Interrupt request 7 (TMS0, TMS1 output) MJT Output Interrupt request 6 (TOP8, TOP9 output) MJT Output Interrupt request 5 (TOP10 output) MJT Output Interrupt request 4 (TIO4 - TIO7 output) MJT Output Interrupt request 3 (TIO8, TIO9 output) MJT Output Interrupt request 2 (TOP0 - TOP5 output) MJT Output Interrupt request 1 (TOP6, TOP7 output) MJT Output Interrupt request 0 (TIO0 - TIO3 output) DMA0-4 Interrupt request SIO1 Receive Interrupt request SIO1 Transmit Interrupt request SIO0 Receive Interrupt request SIO0 Transmit Interrupt request A-D0 Converter Interrupt request DMA5-9 Interrupt request SIO2,3 Transmit/Receive Interrupt request RTD Interrupt request CAN0 Transmit/Receive & Error Interrupt request ICU Vector Table Address H'0000 0094-H'0000 0097 H'0000 0098-H'0000 009B H'0000 009C-H'0000 009F H'0000 00A0-H'0000 00A3 H'0000 00A8-H'0000 00AB H'0000 00AC-H'0000 00AF H'0000 00B0-H'0000 00B3 H'0000 00B4-H'0000 00B7 H'0000 00B8-H'0000 00BB H'0000 00BC-H'0000 00BF H'0000 00C0-H'0000 00C3 H'0000 00C4-H'0000 00C7 H'0000 00C8-H'0000 00CB H'0000 00CC-H'0000 00CF H'0000 00D0-H'0000 00D3 H'0000 00D4-H'0000 00D7 H'0000 00D8-H'0000 00DB H'0000 00DC-H'0000 00DF H'0000 00E8-H'0000 00EB H'0000 00EC-H'0000 00EF H'0000 00F0-H'0000 00F3 H'0000 010C-H'0000 010F 5-13 32171 Group User's Manual (Rev.2.00) 5 Address D0 +0 Address INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table D7 D8 +1 Address D15 H'0000 0094 H'0000 0096 H'0000 0098 H'0000 009A H'0000 009C H'0000 009E H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 MJT Input Interrupt 4 Handler Start Address (A0-A15) MJT Input Interrupt 4 Handler Start Address (A16-A31) MJT Input Interrupt 3 Handler Start Address (A0-A15) MJT Input Interrupt 3 Handler Start Address (A16-A31) MJT Input Interrupt 2 Handler Start Address (A0-A15) MJT Input Interrupt 2 Handler Start Address (A16-A31) MJT Input Interrupt 1 Handler Start Address (A0-A15) MJT Input Interrupt 1 Handler Start Address (A16-A31) MJT Output Interrupt 7 Handler Start Address (A0-A15) MJT Output Interrupt 7 Handler Start Address (A16-A31) MJT Output Interrupt 6 Handler Start Address (A0-A15) MJT Output Interrupt 6 Handler Start Address (A16-A31) MJT Output Interrupt 5 Handler Start Address (A0-A15) MJT Output Interrupt 5 Handler Start Address (A16-A31) MJT Output Interrupt 4 Handler Start Address (A0-A15) MJT Output Interrupt 4 Handler Start Address (A16-A31) MJT Output Interrupt 3 Handler Start Address (A0-A15) MJT Output Interrupt 3 Handler Start Address (A16-A31) MJT Output Interrupt 2 Handler Start Address (A0-A15) MJT Output Interrupt 2 Handler Start Address (A16-A31) MJT Output Interrupt 1 Handler Start Address (A0-A15) MJT Output Interrupt 1 Handler Start Address (A16-A31) MJT Output Interrupt 0 Handler Start Address (A0-A15) MJT Output Interrupt 0 Handler Start Address (A16-A31) Blank addresses are reserved for future use. Figure 5.4.1 ICU Vector Table Memory Map (1/2) 5-14 32171 Group User's Manual (Rev.2.00) 5 Address H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA D0 +0 Address INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table D7 D8 +1 Address D15 DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address (A16-A31) SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address (A16-A31) A-D0 Converter Interrupt Handler Start Address (A0-A15) A-D0 Converter Interrupt Handler Start Address (A16-A31) DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) H'0000 00EC SIO2 Transmit/Receive Interrupt Handler Start Address (A0-A15) H'0000 00EE SIO2 Transmit/Receive Interrupt Handler Start Address (A16-A31) H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15) H'0000 010E CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31) Blank addresses are reserved for future use. RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) Figure 5.4.2 ICU Vector Table Memory Map (2/2) 5-15 32171 Group User's Manual (Rev.2.00) 5 5.5 Description of Interrupt Operation INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, when multiple interrupt requests occur simultaneously, the interrupt controller resolves priority between these interrupt requests following the procedure described below. (a) The ILEVEL values set in the Interrupt Control Register for each interrupt peripheral I/Os are compared with each other. (b) If the ILEVEL values are the same, they are resolved according to the predetermined hardware priority. (c) The ILEVEL value is compared with IMASK value. When multiple interrupt requests occur simultaneously, the interrupt controller first compares their priority levels set in each Interrupt Control Register's ILEVEL bit to select an interrupt request which has the highest priority. If the interrupt requests have the same LEVEL value, they are resolved according to the hardware-fixed priority. The interrupt request thus selected has its ILEVEL value compared with IMASK value and if its priority is higher than the IMASK value, the interrupt controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Mask Register and the Interrupt Control Register's ILEVEL bit (level 7 = disabled) provided for each internal peripheral I/O and the PSW register IE bit. (a) Interrupt requested or not Resolve priority according to interrupt priority levels (ILEVEL) (b) Resolve priority according to hardware priority (c) Compare with IMASK value Accept interrupt if PSW register IE bit =1 (ILEVEL settings) MJT Output Interrupt Level 3 Request 4 MJT Output Interrupt Level 4 Request 3 MJT Output Interrupt Level 5 Request 2 MJT Output Interrupt Level 3 Request 1 DMA0-4 Interrupt Level 1 Request A-D0 Converter Level 3 Interrupt Request Requested Requested Requested Requested Not requested Requested Level 3 Can be accepted when IMASK = 4-7 Hardware-fixed priority Level 3 Level 3 Figure 5.5.1 Example of Priority Resolution When Accepting Interrupt Requests 5-16 32171 Group User's Manual (Rev.2.00) 5 Table 5.5.1 Hardware-fixed Priority Levels Priority Interrupt Request Source High MJT Input Interrupt Request 4 (TIN3 input) MJT Input Interrupt Request 3 (TIN20-TIN23 input) MJT Input Interrupt Request 2 (TIN16-TIN19 input) MJT Input Interrupt Request 1 (TIN0 input) INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation ICU Vector Table Address H'0000 0094-H'0000 0097 H'0000 0098-H'0000 009B H'0000 009C-H'0000 009F H'0000 00A0-H'0000 00A3 Type of Input Source Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Edge-recognized Level-recognized MJT Output Interrupt Request 7 (TMS0,TMS1 output) H'0000 00A8-H'0000 00AB MJT Output Interrupt Request 6 (TOP8,TOP9 output) H'0000 00AC-H'0000 00AF MJT Output Interrupt Request 5 (TOP10 output) MJT Output Interrupt Request 4 (TIO4-TIO7 output) MJT Output Interrupt Request 3 (TIO8, TIO9 output) H'0000 00B0-H'0000 00B3 H'0000 00B4-H'0000 00B7 H'0000 00B8-H'0000 00BB MJT Output Interrupt Request 2 (TOP0-TOP5 output) H'0000 00BC-H'0000 00BF MJT Output Interrupt Request 1 (TOP6, TOP7 output) H'0000 00C0-H'0000 00C3 MJT Output Interrupt Request 0 (TIO0-TIO3 output) DMA0-4 Interrupt Request SIO1 Receive Interrupt Request SIO1 Transmit Interrupt Request SIO0 Receive Interrupt Request SIO0 Transmit Interrupt Request A-D0 Converter Interrupt Request DMA5-9 Interrupt Request SIO2,3 Transmit/Receive Interrupt Request RTD Interrupt Request Low CAN0 Transmit/Receive & Error Interrupt Request H'0000 00C4-H'0000 00C7 H'0000 00C8-H'0000 00CB H'0000 00CC-H'0000 00CF H'0000 00D0-H'0000 00D3 H'0000 00D4-H'0000 00D7 H'0000 00D8-H'0000 00DB H'0000 00DC-H'0000 00DF H'0000 00E8-H'0000 00EB H'0000 00EC-H'0000 00EF H'0000 00F0-H'0000 00F3 H'0000 010C-H'0000 010F 5-17 32171 Group User's Manual (Rev.2.00) 5 ILEVEL values set 0 (ILEVEL="000") 1 (ILEVEL="001") 2 (ILEVEL="010") 3 (ILEVEL="011") 4 (ILEVEL="100") 5 (ILEVEL="101") 6 (ILEVEL="110") 7 (ILEVEL="111") INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.2 ILEVEL Settings and Accepted IMASK Values IMASK values at which interrupts are accepted Accepted when IMASK is 1-7 Accepted when IMASK is 2-7 Accepted when IMASK is 3-7 Accepted when IMASK is 4-7 Accepted when IMASK is 5-7 Accepted when IMASK is 6-7 Accepted when IMASK is 7 Not accepted (interrupts disabled) 5-18 32171 Group User's Manual (Rev.2.00) 5 (1) Branching to the interrupt handler INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing of Internal Peripheral I/O Interrupts by Handler When the CPU accepts an interrupt, control branches to the EIT vector entry after hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry for External Interrupt (EI) is located at address H'0000 0080. This address is where the instruction (not the jump address) for branching to the beginning of the interrupt processing routine for External Interrupt (EI) is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save tthe accumulator as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware: * The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) * The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). * The interrupt request (EI) to the CPU core is dropped. * The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware: * The interrupt request (EI) to the CPU core is dropped. * The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Note: * Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the PSW register IE bit to "1". [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts. 5-19 32171 Group User's Manual (Rev.2.00) 5 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the currently processed interrupt request was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note: * Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, "Typical Handler Operation for Interrupts from Internal Peripheral I/O." 5-20 32171 Group User's Manual (Rev.2.00) 5 EI (External Interrupt) vector entry INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation H'0000 0080 BRA instruction EI (External Interrupt) handler Hardware preprocessing when EIT is accepted (Note 1) Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack [1] Program being executed [2] Interrupt generated Read and save Interrupt Request Mask Register (IMASK) to the stack Read Interrupt Vector Register (IVECT) Read and overwrite Interrupt Request Mask Register (IMASK) H'0080 0004 IMASK [3] H'0080 0000 (Note 2) IVECT [4] (Note 2) (Note 3) [5] [6] [7] Hardware postprocessing when RTE instruction is executed (Note 1) ICU vector table Read ICU vector table H'0000 0094 Set PSW register IE bit to 1 (Note 4) (Note 5) Interrupt handler start address H'0000 0113 Branch to the interrupt handler for each internal peripheral I/O Interrupt handler Interrupt handler [8] [9] [10] Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack Restore general-purpose registers from the stack (Note 4) (Note 2) [11] Restore PSW from the stack [1] to [12]: Processing of EI by interrupt handler Restore BPC from the stack [12] RTE Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. Note 4: To enable multiple interrupts, execute processing in [6] and [9]. Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here, there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register. Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts. Figure 5.5.2 Typical Operation for Interrupts from Internal Peripheral I/O 5-21 32171 Group User's Manual (Rev.2.00) 5 INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation 5.6.1 Acceptance of SBI System Break Interrupt (SBI) is an emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is _______ accepted anytime upon detection of a falling edge on the SBI signal input pin regardless of how the PSW register IE bit is set, and cannot be masked. 5.6.2 SBI Processing by Handler When the system break interrupt generated has been serviced, always be sure to terminate or reset the system without returning to the program that was being executed when the interrupt occurred. SBI (System Break Interrupt) vector entry H'0000 0010 BRA instruction SBI (System Break Interrupt) handler Program being executed Processing to terminate the system . . . . . . SBI generated Terminate or reset the system Note: Do not return to the program that was being executed when the interrupt occurred. Figure 5.6.1 Typical SBI Operation 5-22 32171 Group User's Manual (Rev.2.00) CHAPTER 6 INTERNAL MEMORY 6.1 6.2 6.3 6.4 Outline of the Internal Memory Internal RAM Internal Flash Memory Registers Associated with the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.6 Boot ROM 6.7 Virtual Flash Emulation Function 6.8 Connecting to A Serial Programmer 6.9 Internal Flash Memory Protect Functions 6.10 Precautions to Be Taken When Reprogramming Flash Memory 6 6.1 Outline of the Internal Memory INTERNAL MEMORY 6.1 Outline of the Internal Memory The 32171 internally contains the following types of memory: * 16 Kbyte RAM * 512 Kbyte, 384 Kbyte, or 256 Kbyte flash memory 6.2 Internal RAM Specifications of the 32171's internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Capacity Location address Wait insertion Internal bus connection Dual port Specification 16 Kbytes H'0080 4000 - H'0080 7FFF Operates with no wait states (when using 40 MHz CPU clock) Connected by 32-bit bus By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (Refer to Chapter 14, "Real-Time Debugger.") Note: * At power-on reset, the internal RAM value is indeterminate. (However, if the device is reset and placed out of reset while the VDD pin has 2.0 V to 3.6 V being applied to it, the RAM content before a reset is retained.) 6-2 32171 Group User's Manual (Rev.2.00) 6 6.3 Internal Flash Memory Specifications of the 32171's internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Capacity Location address Specification M32171F4 : 512 Kbytes M32171F3 : 384Kbytes INTERNAL MEMORY 6.3 Internal Flash Memory M32171F2 : 256 Kbytes M32171F4 : H'0000 0000 - H'0007 FFFF M32171F3 : H'0000 0000 - H'0005 FFFF M32171F2 : H'0000 0000 - H'0003 FFFF Operates with no wait states (when using 40 MHz CPU clock) Can be rewritten 100 times Connected by 32-bit bus Virtual flash emulation function is included. (Refer to Section 6.7, "Virtual Flash Emulation Function.") Wait insertion Durability Internal bus connection Other 6.4 Registers Associated with the Internal Flash Memory The diagram below shows a register map associated with the internal flash memory. Address D0 +0 Address D7 Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) D8 +1 Address D15 Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) H'0080 07E0 H'0080 07E2 H'0080 07E4 H'0080 07E6 H'0080 07E8 H'0080 07EA H'0080 07EC H'0080 07EE H'0080 07F0 H'0080 07F2 Virtual Flash L Bank Register 0 (FELBANK0) Virtual Flash S Bank Register 0 (FESBANK0) Virtual Flash S Bank Register 1 (FESBANK1) Blank addresses are reserved for future use. Figure 6.4.1 Register Map Associated with the Internal Flash Memory 6-3 32171 Group User's Manual (Rev.2.00) 6 6.4.1 Flash Mode Register INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory s Flash Mode Register (FMOD) D0 1 2 3 4 5 6 D7 FPMOD The Flash Mode Register (FMOD) is a read-only status register, with its FPMOD bit indicating the status of the FP (Flash Protect) pin. Write to the flash memory is enabled only when FPMOD = 1. Writing to the flash memory when FPMOD = 0 has no effect. 6-4 32171 Group User's Manual (Rev.2.00) 6 6.4.2 Flash Status Registers INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory The 32171 has two registers to indicate the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address: H'0080 07E1), and the other is Flash Status Register 2 (FSTAT2) included in the flash memory itself. When programming or erasing the flash memory, use these two status registers (FSTAT1, FSTAT2) to control the program/erase operations. s Flash Status Register 1 (FSTAT1) D8 9 10 11 12 13 14 D15 FSTAT The Flash Status Register 1 (FSTAT1) is a read-only status register used to know the execution status of whether the flash memory is being programmed or erased. Note: * While FSTAT bit = 0 (Busy), do not manipulate Flash Control Register 4 (FCNT4)'s FRESET bit. 6-5 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory s Flash Status Register 2 (FSTAT2) D8 FBUSY 9 10 ERASE 11 12 13 14 D15 WRERR1 WRERR2 The Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits which indicate the operating condition of the flash memory. (1) FBUSY (Flash Busy) bit (D8) The FBUSY bit is used to determine whether the operation is terminated when programming or erasing the flash memory. When FBUSY = 0, it means the program or erase operation is being executed; when FBUSY = 1, the operation is terminated. (2) ERASE (Auto Erase operating condition) bit (D10) The ERASE bit is used to determine whether execution of the flash memory erase operation has resulted in an error. When ERASE = 0, it means the erase operation terminated normally; when ERASE = 1, the operation terminated in an error. (3) WRERR1 (Program operating condition) bit (D11) The WRERR1 bit is used to determine after completion of execution whether the flash memory program operation resulted in an error. When WRERR1 = 0, it means the program operation terminated normally; when WRERR1 = 1, the operation terminated in an error. The condition under which WRERR1 is set to 1 is when any bit other than those that must be 0 is found to be a 0 by comparison between the write data and the data in the flash memory. 6-6 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory (4) WRERR2 (Program operating condition) bit (D12) The WRERR2 bit is used to determine after execution whether the flash memory program operation resulted in an error. When WRERR2 = 0, it means the program operation terminated normally; when WRERR2 = 1, the operation terminated in an error. The condition under which WRERR2 is set to 1 is when the flash memory could not be programmed to by repeating the program operation a specified number of times. Notes: * This status register is included in the internal flash memory itself, and can be read out by writing the Read Status Command (H'7070) to any address of the flash memory. For details, refer to Section 6.5, "Programming of Internal Flash Memory." * While FBUSY bit = 0 (program/erase in progress), do not manipulate Flash Control Register 4 (FCNT4)'s FRESET bit. 6-7 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.3 Flash Control Registers s Flash Control Register 1 (FCNT1) D0 1 2 3 FENTRY 4 5 6 D7 FEMMOD The Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash Mode Entry) bit (D3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can be entered only when FENTRY = 1. To set the FENTRY bit to 1, write a 0 and then a 1 to the FENTRY bit in succession while the FP pin = high. The FENTRY bit is cleared in the following cases: * When a 0 is written to the FENTRY bit * When the device is reset * When the FP pin changes state from high to low Note: * If while programming or erasing the flash memory, Flash Status Register 1 (FSTAT1)'s FSTAT bit = 0 (Busy) or Flash Status Register 2 (FSTAT2)'s FBUSY bit = 0 (program/ erase in progress), do not clear the FENTRY bit. 6-8 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is located at address H'0000 0080 of the flash memory. When running a flash write/erase program in RAM while the FENTRY bit = 1, the EI vector entry is located at address H'0080 4000 of the RAM, allowing for flash reprogram operation to be controlled using interrupts. Table 6.4.1 Changes of EI Vector Entry by FENTRY FENTRY 0 1 EI Vector Entry Flash memory area Internal RAM area Address H'0000 0080 H'0080 4000 (2) FEMMOD (Virtual Flash Emulation Mode) bit (D7) The FEMMOD bit controls entry to Virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to 1 while the FENTRY bit = 0. (For details, refer to Section 6.7, "Virtual Flash Emulation Function.") 6-9 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory s Flash Control Register 2 (FCNT2) D8 9 10 11 12 13 14 D15 FPROT The Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (to disable erasing or programming of the flash memory). The flash memory protection becomes invalid (unlocked) by setting the FPROT bit to 1, so that any blocks protected by the lock bit can be erased or programmed. To set the FPROT bit to 1, write a 0 and then a 1 to the FPROT bit in succession while the FENTRY bit = 1. Also, the FPROT bit is cleared to 0 in one of the following cases: * A low-level signal entered to the RESET pin * FPROT bit reset by writing 0 * FP pin = low * FENTRY bit cleared to 0 FENTRY=1 YES NO FPROT=0 FENTRY=1 FPROT=0 FPROT is not set to 1 if write cycle to any other area occurs during this time FPROT=1 FPROT=1 Figure 6.4.2 Protection Unlocking Flow 6-10 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory s Flash Control Register 3 (FCNT3) D0 1 2 3 4 5 6 D7 FELEVEL The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands. By setting the FELEVEL bit to 1, the flash memory erase level can be deepened, which will result in an increased reliability margin. 6-11 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory s Flash Control Register 4 (FCNT4) D8 9 10 11 12 13 14 D15 FRESET The Flash Control Register 4 (FCNT4) controls canceling program/erase operation in the middle and initializing each status bit of Flash Status Register 2 (FSTAT2). When the FRESET bit is set to 1, program/erase operation is canceled in the middle and each status bit of FSTAT2 is initialized (H'80). The FRESET bit is effective only when the FENTRY bit = 1. Information on FRESET bit is ignored unless the FENTRY bit = 1. Make sure that when programming or erasing the flash memory, the FRESET bit remains 0. 6-12 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory FENTRY=0 FENTRY=1 Program/erase flash memory NO Error found YES Program/erase terminated normally FRESET=1 FRESET=0 Program/erase flash memory Figure 6.4.3 FCNT4 Register Usage Example 1 (Initializing Flash Status Register 2) Flash programming or erasing timed out Forcibly terminated FRESET=1 FRESET=0 Figure 6.4.4 FCNT4 Register Usage Example 2 (Forcibly terminating flash memory programming/erasing) 6-13 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.4 Virtual Flash L Bank Register s Virtual Flash L Bank Register 0 (FELBANK0) MOD ENL LBANKAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 D0 Note: * This register must always be accessed in halfword. (1) MODENL (Virtual Flash Emulation Enable) bit (D0) The MODENL bit can be set to 1 after entering virtual flash emulation mode (by setting the FEMMOD bit to 1 while the FENTRY bit = 0). This causes the virtual flash emulation function to become effective for the L bank area selected by the LBANKAD bits. (2) LBANKAD (L Bank Address) bits (D8-D14) The LBANKAD bits are provided for selecting one L bank from L banks separated every 8 KB. Use these LBANKAD bits to set the seven bits, A12-A18, of the 32-bit start address of the L bank you want to select. (For details, refer to Section 6.7, "Virtual Flash Emulation Function.") 6-14 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.5 Virtual Flash S Bank Registers s Virtual Flash S Bank Register 0 (FESBANK0) s Virtual Flash S Bank Register 1 (FESBANK1) MOD ENS SBANKAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 D0 Note: * This register must always be accessed in halfword. (1) MODENS (Virtual Flash Emulation Enable) bit (D0) The MODENS bit can be set to 1 after entering virtual flash emulation mode (by setting the FEMMOD bit to 1 while the FENTRY bit = 0). This causes the virtual flash emulation function to become effective for the S bank area selected by the SBANKAD bits. (2) SBANKAD (S Bank Address) bits (D8-D15) The SBANKAD bits are provided for selecting one S bank from S banks separated every 4 KB. Use these SBANKAD bits to set the eight bits, A12-A19, of the 32-bit start address of the S bank you want to select. (For details, refer to Section 6.7, "Virtual Flash Emulation Function.") 6-15 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.5.1 Outline of Programming Flash Memory When programming to the internal flash memory, there are following two methods to use depending on situation: (1) When the write program does not exist in the internal flash memory (2) When the write program already exists in the internal flash memory For (1), set the FP pin = high, MOD0 = high, and MOD1 = low to enter boot mode. In this case, the reset vector entry is located at the beginning of the boot program area (H'8000 0000). (Normally, the reset vector entry is located at the start address of the internal flash memory.) Transfer the "flash write/erase program" from the boot area into the internal RAM using a boot program. After this transfer, jump to the RAM and set the Flash Control Register 1 FENTRY bit to 1 to make the flash memory ready for program(flash E/W enable mode). You now can program to the internal flash memory using the "flash write/erase program" that has been transferred into the internal RAM. For (2), set the FP pin = high, MOD0 = low, and MOD1 = low to enter single-chip mode. Transfer the "flash write/erase program" from the internal flash memory in which it has been prepared beforehand into the internal RAM. After this transfer, jump to the RAM and set the Flash Control Register 1 (FCNT1) FENTRY bit to 1 using a program in the RAM to make the flash memory ready for program(flash E/W enable mode). You now can program to the internal flash memory using the "flash write/erase program" that has been transferred into the internal RAM. Or you can set the FP pin = high, MOD0 = low, and MOD1 = high to enter flash E/W enable mode in external extension mode. When in flash E/W enable mode (FP pin = 1, FENTRY bit = 1), the EIT vector entry for External Interrupt (EI) is moved to the beginning of the internal RAM (H'0080 4000). During normal mode, the EIT vector entry exists in the flash area (H'0000 0080). When using external interrupts (EI) in flash E/W enable mode, write at the beginning of the internal RAM the instruction for branching to the external interrupt (EI) handler that has been transferred into the internal RAM. Also, because the IVECT register which is read out in the external interrupt (EI) handler has stored in it the flash memory address of the ICU vector table, prepare the ICU vector table to be used during flash E/W enable mode in the internal RAM and convert its address from the IVECT register value to the internal RAM address (by, for example, adding an offset) when jumping to the handler. 6-16 32171 Group User's Manual (Rev.2.00) 6 Flash E/W enable mode (FENTRY=1) INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Normal mode (FENTRY=0) H'0000 0000 Internal ROM area H'0000 0000 Internal ROM area EI vector entry (H'0000 0080) H'0080 3FFF H'0080 4000 Internal RAM EI vector entry H'0080 3FFF (H'0080 4000) H'0080 4000 Internal RAM H'00FF FFFF H'00FF FFFF Figure 6.5.1 EI Vector Entry When in Flash E/W Enable Mode 6-17 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (1) When the write program does not exist in the internal flash memory Use a program in the boot ROM located on memory map to program to the flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode. Use this serial transfer when writing to the flash memory using a flash programmer. FP=L or H MOD1= L MOD0=L RESET=L RAM CPU Boot ROM Flash memory M32R/ECU SIO1 Write data External device FP=H MOD1=L MOD0=H RESET=H RAM Flash write /erase program Boot ROM Flash memory M32R/ECU CPU SIO1 Write data External device FP=H MOD1=L MOD0=H RESET=H RAM Flash write /erase program Boot ROM Flash write data M32R/ECU CPU Flash memory SIO1 Write data External device Figure 6.5.2 Procedure for Writing to Internal Flash Memory (when the write program does not exist in the flash memory) 6-18 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Reset singal deasserted (Boot program starts) Mode selected POWER ON Reset signal deasserted Mode selected RESET MOD0 MOD1 FP Settings by boot program FENTRY Writes to flash memory by boot program Figure 6.5.3 Internal Flash Memory Write Timings (when the write program does not exist in the flash memory) 6-19 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory (2) When the write program already exists in the internal flash memory Use the flash write/erase program already stored in the internal flash memory to program to the flash memory. For program to the flash memory, use the internal peripheral circuits according to your programming system. (The data bus, serial I/O, and ports can be used.) The following shows an example for writing to the flash memory by using serial I/O0 in single-chip mode. FP=L or H MOD1= L MOD0=L RAM CPU Boot ROM Flash write program M32R/ECU SIO0 Write data External device FP=H MOD1=L MOD0=L RAM Flash write /erase program Boot ROM Flash memory M32R/ECU CPU SIO0 Write data External device FP=H MOD1= L MOD0=L RAM Flash write /erase program Boot ROM Flash write data M32R/ECU CPU Flash memory SIO0 Write data External device Figure 6.5.4 Procedure for Writing to Internal Flash Memory (when the write program already exists in the flash memory) 6-20 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash rewrite Flash mode starts turned on Flash mode turned off RESET "H" or "L" MOD0 "L" MOD1 "H" or "L" (Single-chip or external extension) FP FENTRY Write to flash memory by flash write/erase program Flash write/erase program transferred to RAM "H" or "L" Settings by flash write/erase program Figure 6.5.5 Internal Flash Memory Write Timings (when the write program already exists in the flash memory) 6-21 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.2 Controlling Operation Mode during Programming Flash The device's operation modes are set by MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be set during flash program. Table 6.5.1 Operation Modes Set during Flash Program FP L H MOD0 L L MOD1 FENTRY L L 0 0 Operation Mode Single-chip mode Reset Vector Entry Start address of flash memory (H'0000 0000) L H L 0 Processor mode Start address of external area (H'0000 0000) L H L L H H 0 0 External extension mode Start address of flash memory (H'0000 0000) H L L 1 Single-chip mode + flash E/W enable Start address of flash memory (H'0000 0000) H H L 0 Boot mode Start address of boot program area (H'8000 0000) H H L 1 Boot mode + flash E/W enable Start address of boot program area (H'8000 0000) H L H 1 External extension mode Start address of + flash E/W enable flash memory (H'0000 0000) -- (Note 1) H H -- (Note 1) reserved (use inhibited) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) Flash area (H'0000 0080) Flash area (H'0000 0080) External area (H'0000 0080) EI Vector Entry Flash area (H'0000 0080) Note 1: The bar "--" denotes "Don't Care." (1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, before entering flash E/W enable mode, you need to transfer the necessary program into the internal RAM and run the program in RAM. 6-22 32171 Group User's Manual (Rev.2.00) 6 (2) Entering flash E/W enable mode INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Flash E/W enable mode can be entered only when the device is operating in single-chip mode or external extension mode. Namely, you can enter flash E/W enable mode only when the FP pin = high and the Flash Control Register 1 (FCNT1) FENTRY bit = 1. You cannot enter flash E/W enable mode when the device is operating in processor mode or the FP pin = low. (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels (high or low) can be verified using the P8 Data Register (Port Data Register, H'00800 0708) MOD0DT and MOD1DT bits. s P8 Data Register (P8DATA) D0 1 2 P82DT 3 P83DT 4 P84DT 5 P85DT 6 P86DT D7 P87DT MOD0DT MOD1DT 6-23 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Enter one of the following modes: * Single-chip mode + flash E/W enable mode * Boot mode + flash E/W enable mode * External extension mode + flash E/W enable mode FMOD(H'0080 07E0) FPMOD P8DATA(H'0080 0708) MOD0DT MOD1DT MOD0, 1 FP pin levels checked OK NO END Transfer E/W program to internal RAM in each mode Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 0 Switched to flash E/W program Set Flash Control Register in SFR area (FCNT1, H'0080 07E2) flash entry (FENTRY) bit to 1 1 s wait (by hardware timer or software timer) Execute flash E/W command and various read commands (Note 1) Jump to flash memory or apply reset Switched to normal mode END Note 1: For details about each command, refer to Section 6.5.3, "Programming Procedure to Internal Flash Memory." Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode 6-24 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.3 Programming Procedure to the Internal Flash Memory To program to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write/erase program that has already been transferred from the flash memory into the internal RAM. In flash E/W enable mode, no data can be read out from the internal flash memory as in normal mode, so you cannot execute a program that exists in the internal flash memory. Therefore, the flash write/erase program must be prepared in the internal RAM before entering flash E/W enable mode. (Once you've entered flash E/W enable mode, you cannot use any command except flash commands to access the flash memory.) To access the internal flash memory in flash memory E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash memory E/W enable mode. Note: * During flash E/W enable mode, the flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash Memory E/W Enable Mode Command Name Read Array command Page Program command Lock Bit Program command Block Erase command Erase All Unlock Block command Read Status Register command Clear Status Register command Read Lock Bit Status command Verify command (Note1 - 4) Issued Command Data H'FFFF H'4141 H'7777 H'2020 H'A7A7 H'7070 H'5050 H'7171 H'D0D0 Note 1: This command is used in conjunction with Lock Bit Program, Block Erase, and Erase All Unlock Block operations. Note 2: Always issue this command successively after the Lock Bit Program, Block Erase, or Erase All Unlock Block command. Note 3: If the Read Array command (H'FFFF) is issued after the Lock Bit Program, Block Erase, or Erase All Unlock Block command, each of those preceding commands is canceled. Note 4: If other than the Verify command (H'D0D0) and Read Array command (H'FFFF) are issued after the Lock Bit Program, Block Erase, or Erase All Unlock Block command, each of those preceding commands terminates in an error without ever being executed. 6-25 32171 Group User's Manual (Rev.2.00) 6 (1) Read Array command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Read mode is entered by writing command data H'FFFF to any address of the internal flash memory. Then read the flash memory address you want to read out, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command. (2) Page Program command Flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To write data to the flash memory (i.e., to program the flash memory), write the program command H'4141 to any address of the internal flash memory and then the program data to the address to which you want to write. With the Page Program command, you cannot program to the protected blocks. Page Program is automatically performed by the internal control circuit, and the completion of programming can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, the next programming can not be performed. (3) Lock Bit Program command Flash memory can be protected against program/erase one block at a time. The Lock Bit Program command is provided for protecting memory blocks. Write the Lock Bit Program command data H'7777 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the block you want to protect, and this memory block is protected against program/erase. To remove protection, disable lock bit-effectuated protection using the Flash Control Register 2 (FCNT2) FPROT bit (see Section 6.4.3, "Flash Control Registers") and erase the block whose protection you want to remove. (The content of this memory block is also erased.) The tables 6.5.3 to 6.5.5 list the target blocks and their specified addresses when writing the Verify command data. 6-26 32171 Group User's Manual (Rev.2.00) 6 Target Block 0 1 2 3 4 5 6 7 8 9 10 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Table 6.5.3 M32171F4 Target Blocks and Specified Addresses Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE Table 6.5.4 M32171F3 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 7 8 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE Table 6.5.5 M32171F2 Target Blocks and Specified Addresses Target Block 0 1 2 3 4 5 6 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE 6-27 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32171F4's Internal Flash Memory Area (512KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF H'0004 0000 64KB H'0004 FFFF H'0005 0000 64KB H'0005 FFFF H'0006 0000 64KB H'0006 FFFF H'0007 0000 64KB H'0007 FFFF Block 10 Block 9 Block 8 Block 7 Even blocks Block 6 Block 5 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB Block 4 Figure 6.5.7 Block Configuration of the M32171F4 Flash Memory 6-28 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32171F3's Internal Flash Memory Area (384KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF H'0004 0000 64KB H'0004 FFFF H'0005 0000 64KB H'0005 FFFF Block 4 Block 5 Even blocks Block 6 Block 7 Block 8 Figure 6.5.8 Block Configuration of the M32171F3 Flash Memory 6-29 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory M32171F2's Internal Flash Memory Area (256KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 16KB 8KB 8KB 32KB Block 0 Block 1 Block 2 Block 3 Uneven blocks 64KB H'0001 FFFF H'0002 0000 64KB H'0002 FFFF H'0003 0000 64KB H'0003 FFFF Block 4 Block 5 Even blocks Block 6 Figure 6.5.9 Block Configuration of the M32171F2 Flash Memory 6-30 32171 Group User's Manual (Rev.2.00) 6 (4) Block Erase command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the Verify command data H'D0D0 to the last even address of the memory block you want to erase (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"). The content of this memory block is erased. With the Block Erase command, you cannot erase the protected blocks. Block Erase is automatically performed by the internal control circuit, and the completion of Block Erase can be verified by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (Refer to Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = 0, you cannot erase the next block. (5) Erase All Unlock Block command The Erase All Unlock Block command erases all memory blocks that are not protected. To erase all unlock blocks, write the command data H'A7A7 to any address of the internal flash memory. Next, write the command data H'D0D0 to any address of the internal flash memory, and all of unprotected memory blocks are erased. (6) Read Status Register command The Read Status Register command reads out the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory write or erase operation has terminated normally or not. To read Flash Status Register 2, write the command data H'7070 to any address of the internal flash memory. Next, read any address of the internal flash memory, and the content of Flash Status Register 2 (FSTAT2) is read out. (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 (FSTAT2) ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to 0. Write the command data H'5050 to any address of the internal flash memory, and Flash Status Register 2 is cleared to 0. If an error occurs when programming or erasing the flash memory and the Flash Status Register 2 (FSTAT2) ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) bit is set to 1, you cannot perform the next program or erase operation unless ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1) or WRERR2 (Program operating condition 2) is cleared to 0. 6-31 32171 Group User's Manual (Rev.2.00) 6 (8) Read Lock Bit Status command INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory. Next, read the last even address of the block you want to check (see Table 6.5.3, Table 6.5.4, and Table 6.5.5, "Target Blocks and Specified Addresses"), and the data you read shows whether or not the target block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit of the data you read are 0s, it means that the target memory block is protected. If the FLBST0 (lock bit 0) bit and FLBST1 (lock bit 1) bit are 1s, it means that the target memory block is not protected. s Lock Bit Status Register (FLBST) FLBST0 FLBST1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 The Lock Bit Status Register is a read-only register, which contains said lock bits independently for each block. 6-32 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the lock bit to 1 (unprotect the block) After setting the Flash Control Register 2 FPROT bit to invalidate lock bit-effectuated protection, use the Block Erase command (H'2020) or Erase All Unprotect Block command (H'A7A7) to erase the memory block you want to unprotect. This is the only way to unprotect a memory block. You cannot set the lock bit alone to 1. c) Status when the lock bit is reset The lock bit is unaffected by a reset or power outage because it is a nonvolatile bit. (9) Execution flow of each command The diagrams below show an execution flow of each command. START Write Read Array command (H'FFFF) to any address of internal flash memory Read the internal flash memory address you want to read END Figure 6.5.10 Read Array 6-33 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Page Program command (H'4141) to any address of internal flash memory. Write data to the internal flash memory address to which you want to write. (Note 1) Increment the previous write address by 2 and write the next data to the new address. NO Programmed for one page ? YES Written to the internal flash memory by Page Program (Note 2) 1 s wait (by hardware timer or software timer) NO FSTAT bit = 1 YES Read any address of internal flash memory to check for program error. (Note 3) TIME OUT ? 0.5s YES Forcibly terminated NO Last address ? YES NO Go to next page END Note 1: Start writing from the beginning of a 256-byte boundary of the flash memory (lower address H'00). Note 2: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 3: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. Figure 6.5.11 Page Program 6-34 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Lock Bit Program command (H'7777) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (Note 1) 1 s wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 0.5s Read any address of internal flash memory to check for program error. (Note 2) YES Forcibly terminated NO END Note 1: When Program operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for program error. Figure 6.5.12 Lock Bit Program 6-35 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Erase command (H'2020) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by Erase program (Note 1) 1 s wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 1s Read any address of internal flash memory to check for erase error. (Note 2) YES Forcibly terminated NO END Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. Figure 6.5.13 Block Erase 6-36 32171 Group User's Manual (Rev.2.00) 6 START INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory Write Erase All Unlock Block command (H'A7A7) to any address of internal flash memory. Write Verify command (H'D0D0) to any address in memory blocks you want to erase. Flash memory contents erased by Erase program (Note 1) 1 s wait (by hardware timer or software timer) NO FSTAT bit = 1 YES TIME OUT ? 10s Read any address of internal flash memory to check for erase error. (Note 2) YES Forcibly terminated NO END Note 1: When Erase operation starts, you have the Read Status Register command automatically entered. (You do not need to enter the Read Status Register command until you issue another command.) Note 2: Examine the Flash Status Register 2 ERASE (Auto Erase operating condition), WRERR1 (Program operating condition 1), and WRERR2 (Program operating condition 2) bits to check for erase error. Figure 6.5.14 Erase All Unlock Block 6-37 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory START Write Read Status command (H'7070) to any address of internal flash memory. Read any address of internal flash memory. END Figure 6.5.15 Read Status Register START Write Clear Status command (H'5050) to any address of internal flash memory. END Figure 6.5.16 Clear Status Register START Write Read Lock Bit Status command (H'7171) to any address of internal flash memory. Read the last even address of the block whose status you want to read. END Figure 6.5.17 Read Lock Bit Status Register 6-38 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory 6.5.4 Flash Program Time (for Reference) The time required for programming to the internal flash memory is shown below for your reference. (1) M32171F4 a) Transfer time by SIO (for a transfer data size of 512 KB) . 1/57600 bps x 1 (frame) x 11 (number of transfer bits) x 512 KB = 100.1 [s] . b) Flash program time . 512 KB/256-byte block x 8 ms = 16.4 [s] . c) Erase time (entire area) . 50 ms x number of blocks = 550 [ms] . d) Total flash program time (entire 512 KB area) * When communicating at 57600 bps using UART, the flash program time can be ignored because it is very short compared to the serial communication time. Therefore, the flash program time can be calculated using the equation below: . . a + c = 101 [s] When programming data to flash memory at high speed by speeding up the serial communication or by other means, the fastest program time possible is as follows: . . b + c = 17 [s] (2) M32171F3 a) Transfer time by SIO (for a transfer data size of 384 KB) . . 1/57600 bps x 1 (frame) x 11 (number of transfer bits) x 384 KB = 75.1 [s] b) Flash program time . 384 KB/256-byte block x 8 ms = 12.3 [s] . c) Erase time (entire area) . 50 ms x number of blocks = 450 [ms] . d) Total flash program time (entire 384 KB area) * When communicating at 57600 bps using UART, the flash program time can be ignored because it is very short compared to the serial communication time. Therefore, the flash program time can be calculated using the equation below: . . a + c = 76 [s] When programming data to flash memory at high speed by speeding up the serial communication or by other means, the fastest program time possible is as follows: . . b + c = 13 [s] 6-39 32171 Group User's Manual (Rev.2.00) 6 (3) M32171F2 INTERNAL MEMORY 6.5 Programming of the Internal Flash Memory a) Transfer time by SIO (for a transfer data size of 256 KB) . 1/57600 bps 1 (frame) 11 (number of transfer bits) 256 KB = 50.1 [s] . b) Flash program time 256 KB/256-byte block 8 ms .. 8.2 [s] = c) Erase time (entire area) . 50 ms number of blocks = 350 [ms] . d) Total flash program time (entire 256 KB area) * When communicating at 57600 bps using UART, the flash program time can be ignored because it is very short compared to the serial communication time. Therefore, the flash program time can be calculated using the equation below: . . a + c = 50.5 [s] When programming data to flash memory at high speed by speeding up the serial communication or by other means, the fastest program time possible is as follows: = b + c .. 8.6 [s] 6-40 32171 Group User's Manual (Rev.2.00) 6 6.6 Boot ROM The table below shows boot memory specifications of the 32171. Table 6.6.1 Boot Memory Specifications Item Capacity Location address Wait insertion Internal bus connection Read Specification 8 Kbytes H'8000 0000 - H'8000 1FFF INTERNAL MEMORY 6.6 Boot ROM Operates with no wait states (with 40 MHz internal CPU memory clock) Connected by 32-bit bus Can only be read when FP = 1, MOD0 = 1, and MOD1 = 0. When read in other modes, indeterminate values are read out. Cannot be accessed for write. Other Because the boot ROM area is a reserved area that can only be used in boot mode, the program cannot be modified. 6-41 32171 Group User's Manual (Rev.2.00) 6 6.7 Virtual-Flash Emulation Function INTERNAL MEMORY 6.7 Virtual Flash Emulation Function The 32171 can map one 8-Kbyte block of internal RAM beginning with the start address into one of 8-Kbyte areas (L banks) of the internal flash memory and can map up to two 4-Kbyte blocks of internal RAM beginning with address H'0080 6000 into one of 4-Kbyte areas (S banks) of the internal flash memory. This capability is referred to as the "virtual-flash emulation" function. This function allows the data located in an 8-Kbyte block or one or two 4-Kbyte blocks of the internal RAM to be switched for use to or from the L or S bank of flash memory specified by the Virtual-Flash Bank Register. Therefore, applications that require changes of data during program operation can have data dynamically changed using 8 or 4 Kbytes of RAM area. The RAM used for virtual-flash emulation can be accessed for read and write from both the internal RAM and the internal flash memory areas. When this function is used in combination with the internal Real Time Debugger (RTD), the data tables created in the internal flash memory can be referenced or rewritten from outside, thus facilitating data table tuning. Before programming to the internal flash memory, always be sure to terminate this virtualflash emulation mode. H'0080 4000 RAM bank L block 0 (FELBANK0) 8Kbytes H'0080 6000 RAM bank S block 0 (FESBANK0) 4Kbytes RAM bank S block 1 (FESBANK1) 4Kbytes H'0080 7000 H'0080 7FFF Figure 6.7.1 Internal RAM Bank Configuration of the 32171 6-42 32171 Group User's Manual (Rev.2.00) 6 6.7.1 Virtual-Flash Emulation Areas INTERNAL MEMORY 6.7 Virtual Flash Emulation Function The following shows the areas effective for the virtual-flash emulation function. Select one of 8-Kbyte blocks or L banks of flash memory using the Virtual-Flash L Bank Register (FELBANK0) (by setting the seven address bits A12-A18 of the start address of the desired L bank in the Virtual-Flash L Bank Register LBANKAD bits). Then set the Virtual-Flash L Bank Register MODENL bit (MODENL0 bit) to 1. The selected L bank area can be rewritten with the 8-Kbyte content of the internal RAM beginning with its start address. Also, select one or two of 4-Kbyte blocks or S banks of flash memory using the Virtual-Flash S Bank Registers (FESBANK0 and FESBANK1) (by setting the eight address bits A12-A19 of the start address of each desired S bank in the Virtual-Flash S Bank Register SBANKAD bits). Then set the Virtual-Flash S Bank Register MODENS0 and MODENS1 bits to 1. The selected S bank areas can be replaced with 4 Kbytes of the internal RAM, for up to two blocks, beginning with the address H'0080 6000. In this way, one 8-Kbyte block or L bank and two 4-Kbyte blocks or S banks for up to a total of three banks can be selected. Notes: * If the virtual-flash emulation enable bit is enabled after setting the same bank area in multiple virtual-flash bank registers, the corresponding internal RAM area (8 or 4 Kbytes) is allocated in order of priority FELBANK0 > FESBANK0 > FESBANK1. * During virtual-flash emulation mode, RAM can be accessed for read and write from the internal RAM area and virtual-flash setup area. * When performing virtual-flash read after setting Flash Control Register 1's Virtual-Flash Emmulation Mode bit to 1, be sure to wait for three CPU clock periods or more before performing virtual-flash read after setting the said bit to 1. * Before performing virtual-flash read after setting the Virtual-flash Bank Register(L Bank and S Bank Registers)'s virtual-flash emulation enable and bank address bits, be sure to insert wait states equal to or greater than three CPU clock periods. 6-43 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8Kbytes) L bank 1 (8Kbytes) L bank 2 (8Kbytes) H'0080 4000 H'0007 C000 H'0007 E000 L bank 62 (8Kbytes) L bank 63 (8Kbytes) Notes: * If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. * When you access the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.2 Virtual-Flash Emulation Areas of the M32171F4 Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4Kbytes) S bank 1 (4Kbytes) S bank 2 (4Kbytes) H'0080 4000 H'0080 6000 H'0080 7000 H'0007 E000 H'0007 F000 S bank 126 (4Kbytes) S bank 127 (4Kbytes) Notes: * If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. * When you access the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0,1, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.3 Virtual-Flash Emulation Areas of the M32171F4 Divided in Units of 4 Kbytes 6-44 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8Kbytes) L bank 1 (8Kbytes) L bank 2 (8Kbytes) H'0080 4000 H'0005 C000 H'0005 E000 L bank 46 (8Kbytes) L bank 47 (8Kbytes) Notes: * If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. * When you access the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.4 Virtual-Flash Emulation Areas of the M32171F3 Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4Kbytes) S bank 1 (4Kbytes) S bank 2 (4Kbytes) H'0080 4000 H'0080 6000 H'0080 7000 H'0005 E000 H'0005 F000 S bank 94 (4Kbytes) S bank 95 (4Kbytes) Notea: * If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. * When you access the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0,1, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.5 Virtual-Flash Emulation Areas of the M32171F3 Divided in Units of 4 Kbytes 6-45 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function H'0000 0000 H'0000 2000 H'0000 4000 L bank 0 (8Kbytes) L bank 1 (8Kbytes) L bank 2 (8Kbytes) H'0080 4000 H'0003 C000 H'0003 E000 L bank 30 (8Kbytes) L bank 31 (8Kbytes) Notes: * If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. * When you access the 8-Kbyte area (L bank) selected by Virtual-Flash L Bank Register 0, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtual-flash memory areas. Figure 6.7.6 Virtual-Flash Emulation Areas of the M32171F2 Divided in Units of 8 Kbytes H'0000 0000 H'0000 1000 H'0000 2000 S bank 0 (4Kbytes) S bank 1 (4Kbytes) S bank 2 (4Kbytes) H'0080 4000 H'0080 6000 H'0080 7000 H'0003 E000 H'0003 F000 S bank 62 (4Kbytes) S bank 63 (4Kbytes) Notes: * If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 or 4 Kbytes) to be allocated is selected by priority: FELBANK0 > FESBANK0 > FESBANK 1. * When you access the 4-Kbyte area (S bank) selected by Virtual-Flash S Bank Register 0, 1, you actually are accessing the internal RAM area. During virtual-flash emulation mode, the RAM can be accessed for read and write from both the internal RAM and the selected virtualflash memory areas. Figure 6.7.7 Virtual-Flash Emulation Areas of the M32171F2 Divided in Units of 4 Kbytes 6-46 32171 Group User's Manual (Rev.2.00) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H'00 H'02 H'04 H'0000 2000 H'0000 4000 L bank 62 L bank 63 H'0007 C000 H'0007 E000 H'7C H'7E Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.8 Values Set in the M32171F4's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) S bank address (SBANKAD) bit set value H'00 H'01 H'02 H'0000 1000 H'0000 2000 S bank 126 S bank 127 H'0007 E000 H'0007 F000 H'7E H'7F Note 1: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.9 Values Set in the M32171F4's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-47 32171 Group User's Manual (Rev.2.00) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H'00 H'02 H'04 H'0000 2000 H'0000 4000 L bank 46 L bank 47 H'0005 C000 H'0005 E000 H'5C H'5E Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.10 Values Set in the M32171F3's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) S bank address (SBANKAD) bit set value H'00 H'01 H'02 H'0000 1000 H'0000 2000 S bank 94 S bank 95 H'0005 E000 H'0005 F000 H'5E H'5F Note 1: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.11 Values Set in the M32171F3's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-48 32171 Group User's Manual (Rev.2.00) 6 L bank L bank 0 L bank 1 L bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) INTERNAL MEMORY 6.7 Virtual Flash Emulation Function L bank address (LBANKAD) bit set value H'00 H'02 H'04 H'0000 2000 H'0000 4000 L bank 30 L bank 31 H'0003 C000 H'0003 E000 H'3C H'3E Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register's L bank address (LBANKAD) bits. Figure 6.7.12 Values Set in the M32171F2's Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank S bank 0 S bank 1 S bank 2 Start address of bank in flash memory H'0000 0000 (Note 1) S bank address (SBANKAD) bit set value H'00 H'01 H'02 H'0000 1000 H'0000 2000 S bank 62 S bank 63 H'0003 E000 H'0003 F000 H'3E H'3F Note 1: Set the eight bits A12-A19 of the start address (32-bit) of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits. Figure 6.7.13 Values Set in the M32171F2's Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6-49 32171 Group User's Manual (Rev.2.00) 6 6.7.2 Entering Virtual Flash Emulation Mode INTERNAL MEMORY 6.7 Virtual Flash Emulation Function To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function. Even during virtual-flash emulation mode, the internal RAM area (H'0080 4000 through H'0080 7FFF) can be accessed as internal RAM. Setup start Write flash data to RAM Go to Virtual Flash Emulation Mode FEMMOD 1 Set RAM location address in Virtual Flash Bank Register LBANKAD Address A12-A18 SBANKAD Address A12-A19 Enable Virtual Flash Emulation Function MODENL 1 MODENS 1 End of Setting Figure 6.7.14 Virtual-flash Emulation Mode Sequence 6-50 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.7 Virtual Flash Emulation Function 6.7.3 Application Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Flash Bank xx Initial value Replace area RAM block 0 RAM block 1 Data write to RAM0 (2) Program operation using RAM block 0 Flash Replace Bank xx Initial value RAM block 0 Bank xx specified RAM block 0 RAM block 1 Data write to RAM1 (3) Program operation changed from RAM block 0 to RAM block 1 Flash Replace Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified (settings invalid) Bank xx specified RAM block 0 RAM block 1 Figure 6.7.15 Application Example of Virtual Flash Emulation (1/2) 6-51 32171 Group User's Manual (Rev.2.00) 6 (4) Program operation using RAM block 1 Flash INTERNAL MEMORY 6.7 Virtual Flash Emulation Function Replace Bank xx Initial value RAM block 1 Bank xx specified RAM block 0 RAM block 1 Data write to RAM0 (5) Program operation changed from RAM block 1 to RAM block 0 Flash Replace Bank xx Initial value RAM block 0 RAM block 1 Bank xx specified (settings invalid) Bank xx specified RAM block 0 RAM block 1 (6) Go to item (2) NOTE : valid area Figure 6.7.16 Application Example of Virtual Flash Emulation (2/2) 6-52 32171 Group User's Manual (Rev.2.00) 6 6.8 Connecting to A Serial Programmer INTERNAL MEMORY 6.8 Connecting to A Serial Programmer When you reprogram the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32171 shown below to make them suitable for the serial programmer. Table 6.8.1 Processing the 32171 Pins when Using a Serial Programmer Pin Name SCLKI1 RXD1 Pin Number 71 70 Function Transfer clock input Serial data input (receive data) Serial data output (transmit data) Transmit/receive enable output Flash memory protect Operation mode 0 Operation mode 1 Reset Clock input Clock output PLL circuit control input PLL circuit power supply PLL circuit ground A-D converter reference voltage input Remark Need to be pulled high Need to be pulled high TXD1 P84 FP MOD0 MOD1 RESET XIN XOUT VCNT OSC-VCC OSC-VSS VREF0 AVCC0 AVSS0 FVCC VDD VCCE VCCI VSS 69 68 94 92 93 91 4 5 7 6 3 42 43 60 73 108 20, 65, 95, 132 61, 123, 137 21, 62, 72, 96, 138 Need to be pulled high Connect to ground Connect to 3.3 V power supply Connect to ground Connect to 5 V power supply Connect to 5 V power supply Connect to ground Connect to 3.3 V power supply Connect to 3.3 V power supply Analog power supply Analog ground Flash memory power supply RAM backup power supply 5 V power supply 3.3 V power supply Ground Note: All other pins do not need to be processed. 6-53 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.8 Connecting to A Serial Programmer The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer programs to the flash memory in clock-synchronized serial mode. No communication problems associated with the oscillation frequency may occur. If the system uses any 32171 pins which will connect to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H'0000 0084 through H'0000 0093 as an area to check ID for flash memory protection. User system circuit board Connects to 5 V power supply AVCC0 VCCE VREF0 Connects to 3.3 V power supply FVCC Connects to 5 V power supply VCCI OSC-VCC VDD Various signals on flash programmer 5V(Input) RxD(Input) TxD(Output) SCLKO(Output) BUSY(Input) MOD0(Output) FP(Output) RESET(Output) GND(Output) P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET VSS AVSS0 OSC-VSS To system circuit about 2K MOD1 JTRST Connector Set microcomputer operating conditions XIN XOUT VCNT 32171 Notes: * Turn on the power to the user system before you program to the flash memory. * If the system circuit uses P84-P87, consideration must be taken for connection of a serial programmer. * P64/SBI must be fixed high or low to ensure that interrupts will not be generated. * The pullup resistances of P84, P86, and P87 must be set to suit system design conditions. * The typical pullup resistances of P84, P86, and P87 are 4.7 to 10 k. * All other ports, whether high or low, do not affect flash memory programming. Figure 6.8.1 Pin Connection Diagram 6-54 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.9 Internal Flash Memory Protect Functions 6.9 Internal Flash Memory Protect Functions The 32171's internal flash memory has the following four protect functions to prevent unintended reprogramming by an erratic operation or unauthorized copying or reprogramming of its contents. (1) Flash memory protect ID When using flash memory reprogramming tools such as a general-purpose serial programmer or an emulator, the ID entered from the keyboard is checked against the flash memory's internal ID. In no case can reprogramming be executed unless the correct ID is entered. (For some tools, erasing of the entire area only can be executed.) (2) Protection by FP pin The flash memory is protected in hardware against E/W by pulling the FP (Flash Protect) pin low. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)'s FPMOD (external FP pin status) bit in a flash write program, the flash memory can also be protected in software. For systems that do not require protection by external pin settings, holding the FP pin high will help to simplify operation while reprogramming the flash memory. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered unless Flash Control Register 1 (FCNT1)'s FENTRY (flash mode entry) bit is set to 1. Furthermore, the FENTRY bit can only be set to 1 by writing 0 and 1 in succession while the FP pin is high. (4) Protection by a lock bit Each block of flash memory has a lock bit, so that any memory block can be protected against E/W by setting this bit to 0. 6-55 32171 Group User's Manual (Rev.2.00) 6 INTERNAL MEMORY 6.10 Precautions to Be Taken When Reprogramming Flash Memory 6.10 Precautions to Be Taken When Reprogramming Flash Memory The following describes precautions to be taken when you reprogram the flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode. * When reprogramming the flash memory, a high voltage is generated inside the chip. Because this high voltage could cause the chip to break down, be careful about mode pin and power supply management not to move from one mode to another while reprogramming. * If the system uses any pin that is to be used by a general-purpose reprogramming tool, take appropriate measures to prevent adverse effects when connecting the tool. * If flash memory protection is needed when using a general-purpose reprogramming tool, set any ID in the flash memory protect ID check area (H'0000 0084-H'0000 0093). * If flash memory protection is not needed when using a general-purpose reprogramming tool, set H'FF in the entire flash memory protect ID check area (H'0000 0084-H'0000 0093). * Before using a reset by Flash Control Register 4 (FCNT4)'s FRESET bit to clear each error status in Flash Status Register 2 (FSTAT2) (initialized to H'80), check to see that Flash Status Register 1 (FSTAT1)'s FSTAT bit = 1 (Ready). * Before changing Flash Control Register 1 (FCNT1)'s FENTRY bit from 1 to 0, check to see that Flash Status Register 1 (FSTAT1)'s FSTAT bit = 1 (Ready) or Flash Status Register 2 (FSTAT2)'s FBUSY bit = 1 (Ready). * If Flash Control Register 1 (FCNT1)'s FENTRY bit = 1 and Flash Status Register 1 (FSTAT1)'s FSTAT bit = 0 (Busy) or Flash Status Register 2 (FSTAT2)'s FBUSY bit = 0 (program/erase in progress), do not clear the FENTRY bit. 6-56 32171 Group User's Manual (Rev.2.00) CHAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State after Exiting Reset 7.4 Things To Be Considered after Exiting Reset 7 7.1 Outline of Reset _____ RESET 7.1 Outline of Reset The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out _____ of a reset state by releasing the RESET input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the program starts executing from the reset vector entry. 7.2 Reset Operation 7.2.1 Reset at Power-on _____ When powering on the device, hold the RESET input low until its internal multiply-by-4 clock generator becomes oscillating stably. 7.2.2 Reset during Operation _____ To reset the device during operation, hold the RESET input low for more than four clock periods of XIN signal. 7.2.3 Reset Vector Relocation during Flash Reprogramming When placed in boot mode, the reset vector entry address is moved to the start address of the boot program space (address H'8000 0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory." 7-2 32171 Group User's Manual (Rev.2.00) 7 7.3 Internal State after Exiting Reset RESET 7.3 Internal State after Exiting Reset The table below lists the register state of the device after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section in this manual where the relevant internal peripheral I/O is described. Table 7.3.1 Internal State after Exiting Reset Register PSW CBR SPI SPU BPC PC R0-R15 (CR0) (CR1) (CR2) (CR3) (CR6) State after Exiting Reset B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, BC bits = indeterminate) H'0000 0000 (C bit = 0) Indeterminate Indeterminate Indeterminate H'0000 0000 (Executed beginning with address H'0000 0000) (Note 1) Indeterminate ACC (accumulator) Indeterminate RAM Indeterminate at power-on reset (However, if the device is reset and placed out of reset while the VDD pin has 2.0 V to 3.6 V being applied to it, the RAM content before a reset is retained.) Note 1: When in boot mode, this changes to the start address of the boot program space (H'8000 0000). 7-3 32171 Group User's Manual (Rev.2.00) 7 RESET 7.3 Internal State after Exiting Reset The pins that were set for input when reset go to a high-impedance state (Hi-Z). Here, "when reset" means that the RESET# pin input is held low (the device being reset) and is released back high (the device being placed out of reset). Table 7.3.2 Pin Status When Reset (1/4) Function PIN NO. 1 2 3 4 5 6 7 8 Pin Name Port P221/CRX (Note 1) P225/A12 OSC-VSS XIN XOUT OSC-VCC VCNT P30/A15 P221 P225 P30 Other than Other than port port CRX A12 OSC-VSS XIN XOUT OSC-VCC VCNT A15 Input/output Input Condition Pin status when reset function Input/output Status during Status after exiting reset reset P221 Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Input Hi-z Hi-z Hi-z XOUT Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Indeterminate Hi-z Hi-z Hi-z Hi-z Indeterminate XOUT P225 During single-chip mode Input/output During external extension or A12 processor mode OSC-VSS Input Output During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode XIN XOUT OSC-VCC VCNT P30 A15 P31 A16 P32 A17 P33 A18 P34 A19 P35 A20 P36 A21 P37 A22 P20 A23 P21 A24 P22 A25 P23 A26 VCCE VSS P24 A27 P25 A28 P26 A29 P27 A30 P00 DB0 9 P31/A16 P31 A16 - 10 P32/A17 P32 A17 - 11 P33/A18 P33 A18 - 12 P34/A19 P34 A19 - 13 P35/A20 P35 A20 - 14 P36/A21 P36 A21 - 15 P37/A22 P37 A22 - 16 P20/A23 P20 A23 - 17 P21/A24 P21 A24 - 18 P22/A25 P22 A25 - 19 20 21 22 P23/A26 VCCE VSS P24/A27 P23 P24 A26 VCCE VSS A27 - 23 P25/A28 P25 A28 - 24 P26/A29 P26 A29 - 25 P27/A30 P27 A30 - 26 P00/DB0 P00 DB0 - Note 1: P221 is used exclusively for CAN input 7-4 32171 Group User's Manual (Rev.2.00) 7 Table 7.3.3 Pin Status When Reset (2/4) Pin NO. Pin Name Port P01 Function Other than Other than Input/output port port DB1 - RESET 7.3 Internal State after Exiting Reset Pin status when reset Condition Function Input/output Status during Status after exiting reset reset P01 DB1 P02 DB2 P03 DB3 P04 DB4 P05 DB5 P06 DB6 P07 DB7 P10 DB8 P11 DB9 P12 DB10 P13 DB11 P14 DB12 P15 DB13 P16 DB14 P17 DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - 27 P01/DB1 28 P02/DB2 P02 DB2 - 29 P03/DB3 P03 DB3 - 30 P04/DB4 P04 DB4 - 31 P05/DB5 P05 DB5 - 32 P06/DB6 P06 DB6 - 33 P07/DB7 P07 DB7 - 34 P10/DB8 P10 DB8 - 35 P11/DB9 P11 DB9 - 36 P12/DB10 P12 DB10 - 37 P13/DB11 P13 DB11 - 38 P14/DB12 P14 DB12 - 39 P15/DB13 P15 DB13 - 40 P16/DB14 P16 DB14 - 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 P17/DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI P17 - DB15 VREF0 AVCC0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 AVSS0 VCCI - During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input - 7-5 32171 Group User's Manual (Rev.2.00) 7 Table 7.3.4 Pin Status When Reset (3/4) Function Pin NO. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 VSS P174/TXD2 P175/RXD2 VCCE P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 VSS FVCC P61 P62 P63 P64/SBI (Note 1) P70/BCLK/WR P71/WAIT P72/HREQ P73/HACK P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK P93/TO16 P94/TO17 P95/TO18 P96/TO19 P97/TO20 RESET MOD0 MOD1 FP VCCE VSS P110/TO0 P111/TO1 Pin Name Port P174 P175 P82 P83 P84 P85 P86 P87 P61 P62 P63 P64 P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 P96 P97 P110 P111 P112 P113 P114 P115 P116 P117 P100 P101 P102 P103 P104 P105 P106 P107 P124 P125 Other than Other than port port VSS TXD2 RXD2 VCCE TXD0 RXD0 SCLKI0 TXD1 RXD1 SCLKI1 VSS FVCC SBI BCLK WAIT HREQ HACK RTDTXD RTDRXD RTDACK RTDCLK TO16 TO17 TO18 TO19 TO20 RESET MOD0 MOD1 FP VCCE VSS TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TO8 TO9 TO10 VDD JTMS JTCK JTRST JTDO JTDI TO11 TO12 TO13 TO14 TO15 TCLK0 TCLK1 ______ RESET 7.3 Internal State after Exiting Reset Pin status when reset Input/output Input/output Input/output Condition Function Input/output Status during Status after reset exiting reset VSS P174 P175 VCCE P82 P83 P84 P85 P86 P87 VSS FVCC P61 P62 P63 SBI P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 P96 P97 RESET MOD0 MOD1 FP VCCE VSS P110 P111 P112 P113 P114 P115 P116 P117 P100 P101 P102 VDD JTMS JTCK JTRST JTDO JTDI P103 P104 P105 P106 P107 P124 P125 input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input Output input input input input input input input input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z - Input/output Input/output SCLKO0 Input/output Input/output Input/output SCLKO1 Input/output Input/output WR Input/output Input/output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output 99 P112/TO2 100 P113/TO3 101 P114/TO4 102 P115/TO5 103 P116/TO6 104 P117/TO7 105 P100/TO8 106 P101/TO9 107 P102/TO10 108 VDD 109 JTMS (Note 2) 110 JTCK (Note 2) 111 JTRST (Note 2) 112 JTDO (Note 2) 113 JTDI (Note 2) 114 P103/TO11 115 P104/TO12 116 P105/TO13 117 P106/TO14 118 P107/TO15 119 P124/TCLK0 120 P125/TCLK1 Note 1: P64 is used exclusively for SBI input. ____________ Note 2: The JTCK, JTDI, JTDO, and JTMS pins are reset by the JTRST pin, and not by the RESET pin. All of these pins are placed in the high-impedance state while the JTRST pin input is held low. 7-6 32171 Group User's Manual (Rev.2.00) 7 Table 7.3.5 Pin Status When Reset (4/4) Function Pin NO. Pin Name Port 121 P126/TCLK2 122 P127/TCLK3 123 VCCI 124 P130/TIN16 125 P131/TIN17 126 P132/TIN18 127 P133/TIN19 128 P134/TIN20 129 P135/TIN21 130 P136/TIN22 131 P137/TIN23 132 VCCE 133 P150/TIN0 134 P153/TIN3 135 P41/BLW/BLE P126 P127 P130 P131 P132 P133 P134 P135 P136 P137 P150 P153 P41 Other than Other than port Port TCLK2 TCLK3 VCCI TIN16 TIN17 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 VCCE TIN0 TIN3 BLW BLE Input/output RESET 7.3 Internal State after Exiting Reset Pin status when reset Condition Function Input/output Status during Status after exiting reset reset P126 P127 VCCI P130 P131 P132 P133 P134 P135 P136 P137 VCCE P150 P153 P41 BLW P42 BHW VCCI VSS P43 RD P44 CS0 P45 CS1 P46 A13 P47 A14 P220 Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z "H" level Hi-z "H" level Hi-z "H" level Hi-z "H" level Hi-z "H" level Hi-z Indeterminate Hi-z Indeterminate Hi-z Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode During single-chip mode Input/output During external extension or processor mode Input/output 136 P42/BHW/BHE 137 VCCI 138 VSS 139 P43/RD P42 P43 BHW VCCI VSS RD BHE - 140 P44/CS0 P44 CS0 - 141 P45/CS1 P45 CS1 - 142 P46/A13 P46 A13 - 143 P47/A14 144 P220/CTX P47 P220 A14 CTX - 7-7 32171 Group User's Manual (Rev.2.00) 7 RESET 7.4 Things To Be Considered after Exiting Reset 7.4 Things To Be Considered after Exiting Reset * Input/output ports After exiting reset, the 32171's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, enable them for input using the Port Input Function Enable Register (PIEN) PIEN0 bit. For details, refer to Section 8.3, "Input/ Output Port Related Registers." 7-8 32171 Group User's Manual (Rev.2.00) CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits 8.5 Precautions on Input/output Ports 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32171 has a total of 97 input/output ports consisting of P0-P13, P15, P17, and P22 (with P5 reserved for future use, however). These input/output ports can be used as input ports or output ports by setting up the direction registers. Each input/output port serves as a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or external extension bus signal line. Pin functions are selected depending on the device's operation mode you choose or by setting the input/output port's Operation Mode Register. (If any internal peripheral I/O has still another function, you need to set the register provided for that peripheral I/O.) As a new function, the 32171 internally contains a Port Input Function Enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash rewrite. To use any ports in input mode, you need to set the Port Input Function Enable bit accordingly. The input/output ports are outlined in the next pages. 8-2 32171 Group User's Manual (Rev.2.00) 8 Item Number of ports Specification Total 97 lines P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P15 P17 : : : : : : : : : : : : : : : INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports Table 8.1.1 Outline of Input/Output Ports P00 - P07 P10 - P17 P20 - P27 P30 - P37 P41 - P47 P61 - P64 P70 - P77 P82 - P87 P93 - P97 P100 - P107 P110 - P117 P124 - P127 P130 - P137 P150 , P153 P174, P175 (8 lines) (8 lines) (8 lines) (8 lines) (7 lines) (4 lines) (8 lines) (6 lines) (5 lines) (8 lines) (8 lines) (4 lines) (8 lines) (2 lines) (2 lines) P22 : Port function P220, P221, P225 (3 lines) The input/output ports can individually be set for input or output mode using the Direction Control Register provided for each input/output port. (However, P64 is a ___ SBI input-only port and P221 is a CAN input-only port.) Pin function Shared with peripheral I/O or external extension signals to serve dual functions (or with two or more peripheral I/O functions to serve multiple functions) Pin function switchover P0 - P4, P225 : Depends on CPU operation mode (determined by setting MOD0 and MOD1 pins) P6 - P22 : As set by each input/output port's Operation Mode Register (However, peripheral I/O pin functions are selected by peripheral I/O registers.) Note: * P14, P16, and P18-P21 are nonexistent. 8-3 32171 Group User's Manual (Rev.2.00) 8 8.2 Selecting Pin Functions INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions Each input/output port serves dual purposes along with other internal peripheral I/Os or external extension bus signal lines (or triple purposes along with multiple functions of peripheral I/O). Pin functions are selected according to the operation modes set or using the input/output port operation mode registers. When the selected CPU operation mode is external extension mode or processor mode, P0-P4 and P225 all are switched to signal pins for external access. The operation mode is determined depending on how MOD0 and MOD1 pins are set. (See the table below.) Table 8.2.1 CPU Operation Modes and P0-P4 and P225 Pin Functions MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCC Operation Mode Single-chip mode External extension mode External extension signal pin Processor mode Reserved (Use inhibited) -- Pin Functions of P0-P4, P225 input/output port pin Note: * VCCE = 5 V or 3.3 V and VSS = GND. Ports P6-P13, P15, P17, and P22 (except for P64, P221, P225) have their pin functions switched between input/output ports and internal peripheral I/Os by setting up the input/output port operation mode registers. If any internal peripheral I/O has multiple functions, select the desired pin function using the relevant internal peripheral I/O register. Operation on FP and MOD1 pins during write to the internal flash memory does not affect the pin functions. 8-4 32171 Group User's Manual (Rev.2.00) 8 0 P0 P1 Settings of CPU operation mode P2 (Note 1) P3 P4 (Reserved) DB0 DB8 A23 A15 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 1 DB1 DB9 A24 A16 BLW/ BLE 2 DB2 DB10 A25 A17 BHW/ BHE 3 DB3 DB11 A26 A18 RD 4 DB4 DB12 A27 A19 CS0 5 DB5 DB13 A28 A20 CS1 6 DB6 DB14 A29 A21 A13 7 DB7 DB15 A30 A22 A14 P5 P6 P7 P8 P9 P10 P11 P12 TO8 TO0 TO9 TO1 TO10 TO2 BCLK/ WR (P61) WAIT (P62) HREQ TXD0 (P63) HACK RXD0 TO16 TO11 TO3 SBI RTDTXD RTDRXD RTDACK RTDCLK SCLKI0/ SCLKO0 TXD1 TO18 TO13 TO5 TCLK1 TIN21 RXD1 TO19 TO14 TO6 TCLK2 TIN22 SCLKI1/ SCLKO1 TO17 TO12 TO4 TCLK0 TO20 TO15 TO7 TCLK3 TIN23 P13 Settings of input/ output port Operation Mode P14 Register P15 P16 P17 P18 P19 P20 P21 P22 TIN16 TIN17 TIN18 TIN19 TIN20 TIN0 TIN3 TXD2 RXD2 CTX CRX A12 (Note 2) Note 1: Pin functions are switched over by setting MOD0 and MOD1 pins. Note 2: Pin functions are switched over by setting MOD0 and MOD1 pins. Also, use of this pin requires caution because it has a debug event function. Note: * P14, P16, P18, P19, P20 and P21 have no functions assigned in M32171. Figure 8.2.1 Input/Output Ports and Pin Function Assignments 8-5 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers The input/output port related registers consist of the Port Data Register, Port Direction Register, and Port Operation Mode Register. Of these, the Port Operation Mode Register is available for only P7-P22. Ports P0-P4 and P225 have their pin functions determined depending on CPU operation mode (selected by FP, MOD0, and MOD1 pins). Port P5 is reserved for future use. An input/output port related register map is shown below. Address +0 Address +1 Address D0 D7 D8 D15 H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P1 Data Register (P1DATA) P3 Data Register (P3DATA) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P22 Data Register (P22DATA) H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P22 Direction Register (P22DIR) Blank addresses are reserved. Note : * The Data Register, Direction Register, and Operation Mode Register for P14, P16, and P18-P21 are not included. Figure 8.3.1 Input/Output Port Related Register Map (1/2) 8-6 32171 Group User's Manual (Rev.2.00) 8 Address H'0080 0744 H'0080 0746 D0 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers +0 Address D8 +1 Address D15 Port Input Function Enable Register (PIEN) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) H'0080 0748 P8 Operation Mode Register (P8MOD) H'0080 074A P10 Operation Mode Register (P10MOD) H'0080 074C P12 Operation Mode Register (P12MOD) H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 P22 Operation Mode Register (P22MOD) Blank addresses are reserved. 8.3.2 Input/Output Port Related Register Map (2/2) 8-7 32171 Group User's Manual (Rev.2.00) 8 8.3.1 Port Data Registers s P0 Data Register (P0DATA) s P1 Data Register (P1DATA) s P2 Data Register (P2DATA) s P3 Data Register (P3DATA) s P4 Data Register (P4DATA) s P6 Data Register (P6DATA) s P7 Data Register (P7DATA) s P8 Data Register (P8DATA) s P9 Data Register (P9DATA) s P10 Data Register (P10DATA) s P11 Data Register (P11DATA) s P12 Data Register (P12DATA) s P13 Data Register (P13DATA) s P15 Data Register (P15DATA) s P17 Data Register (P17DATA) s P22 Data Register (P22DATA) D0 ( D8 Pn0DT 1 9 Pn1DT 2 10 Pn2DT INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 3 11 Pn3DT 4 12 Pn4DT 5 13 Pn5DT 6 14 Pn6DT D7 D15 ) Pn7DT Note: * n = 0-13, 15, 17, and 22 (not including P5). Notes: * The bits listed below have no functions assigned. (They show a 0 when read; writing to these bits has no effect.) P40, P60, P65-P67, P90-P92, P120-P123, P151, P152, P154-P157, P170-P173, P176, P177, P222P224, P226, P227 : * Port P64 is available for only input mode. Writing to P64DT bit has no effect. : * Ports P80 and P81 are available for only input mode. Writing to P80DT and P81DT bits has no effect. When read, P80 and P81 show the MOD0 and MOD1 pin levels, respectively. : * Port P221 is available for only input mode. Writing to P221DT bit has no effect. : * P14, P16, and P18-P21 do not have data registers. 8-8 32171 Group User's Manual (Rev.2.00) 8 8.3.2 Port Direction Registers INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P0 Direction Register (P0DIR) s P1 Direction Register (P1DIR) s P2 Direction Register (P2DIR) s P3 Direction Register (P3DIR) s P4 Direction Register (P4DIR) s P6 Direction Register (P6DIR) s P7 Direction Register (P7DIR) s P8 Direction Register (P8DIR) s P9 Direction Register (P9DIR) s P10 Direction Register (P10DIR) s P11 Direction Register (P11DIR) s P12 Direction Register (P12DIR) s P13 Direction Register (P13DIR) s P15 Direction Register (P15DIR) s P17 Direction Register (P17DIR) s P22 Direction Register (P22DIR) D0 ( D8 Pn0DIR 1 9 Pn1DIR 2 10 Pn2DIR 3 11 Pn3DIR 4 12 Pn4DIR 5 13 Pn5DIR 6 14 Pn6DIR D7 D15 ) Pn7DIR Note: * n = 0-13, 15, 17, and 22 (not including P5). Notes: * he bits listed below have no functions assigned. (They show a 0 when read; writing to these bits has no effect.) P40, P60, P65-P67, P90-P92, P120-P123, P151, P152, P154-P157, P170-P173, P176, P177, P222-P224, P226, P227 : * When reset, all ports are placed in input mode. : * Port P64 is input mode-only. The register does not have a P64DIR bit. : * Port P221 is input mode-only. The register does not have a P221DIR bit. : * Ports P80 and P81 are input mode-only. The register does not have P80DIR and P81DIR bits. : * P14, P16, and P18-P21 do not have data registers. 8-9 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode Registers s P7 Operation Mode Register (P7MOD) D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD __ R W 1 : BCLK / WR 0 : P71 ____ 1 : WAIT 0 : P72 ____ 1 : HREQ 0 : P73 ____ 1 : HACK 0 : P74 1 : RTDTXD 0 : P75 1 : RTDRXD 0 : P76 1 : RTDACK 0 : P77 1 : RTDCLK 8-10 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P8 Operation Mode Register (P8MOD) D0 1 2 3 4 5 6 D7 P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD 8-11 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P9 Operation Mode Register (P9MOD) D8 9 10 11 12 13 14 D15 P93MOD P94MOD P95MOD P96MOD P97MOD 8-12 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P10 Operation Mode Register (P10MOD) D0 1 2 3 4 5 6 D7 P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD 8-13 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P11 Operation Mode Register (P11MOD) D8 9 10 11 12 13 14 D15 P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD 8-14 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P12 Operation Mode Register (P12MOD) D0 1 2 3 4 5 6 D7 P124MOD P125MOD P126MOD P127MOD 8-15 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P13 Operation Mode Register (P13MOD) D8 9 10 11 12 13 14 D15 P130MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD 8-16 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P15 Operation Mode Register (P15MOD) D8 P150MOD 9 10 11 P153MOD 12 13 14 D15 Note: * Ports P151, P152, and P154-157 are nonexistent. 8-17 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P17 Operation Mode Register (P17MOD) D8 9 10 11 12 13 14 D15 P174MOD P175MOD Note : * Ports P170-P173, and P176, P177 are nonexistent. 8-18 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s P22 Operation Mode Register (P22MOD) D0 P220MOD 1 2 3 4 5 P225MOD 6 D7 Notes: * P221 is a CAN input-only pin. : * The pin function of P225 changes depending on how MOD0 and MOD1 pins are set. Also, because it has a debug event function, be careful when using this port. : * P222-224, P226, and P227 are nonexistent. 8-19 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers s Port Input Function Enable Register (PIEN) D8 9 10 11 12 13 14 D15 PIEN0 This register is provided to prevent current from flowing into the port input pin. Because after reset this register is set to disable input, it must be set to 1 before input can be processed. During boot mode, all pins shared with serial I/O function are enabled for input, so that when rewriting the flash memory via serial communication, you can set this register to 0 to prevent current from flowing in from any pins other than serial I/O function. The next page lists the pins that can be controlled by the Port Input Function Enable Register in each mode. 8-20 32171 Group User's Manual (Rev.2.00) 8 Mode Name INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Table 8.3.1 Controllable Pins by Port Function Enable Bit Controllable Pins P00 - P07, P10 - P17, P20 - P27 P30 -P37 , P41 - P47, P61 - P63 Single chip P70 - P77, P82 - P87, P93 - P97 P100 - P107, P110 - P117, P124 - P127 P130 - P137, P150, P153, P174, P175 P220, P225 P61 - P63, P70 - P77, P82 - P87 External extension Microprocessor P93 - P97, P100 - P107, P110 - P117 P124 - P127, P130 - P137 P150, P153, P174, P175, P220 P00 - P07, P10 - P17, P20 - P27 P30 -P37 , P41 - P47, P61 - P63 Boot (single chip) P67, P70 - P77, P93 - P97 P100 - P107, P110 - P117, P124 - P127 P130 - P137, P150, P153, P220, P225 P00 - P07, P10 - P17 P20 - P27, P30 - P37 P41 - P47, P64, P221 P225, FP P64, P82 - P87 P174, P175, P221, FP Noncontrollable Pins P64, P221, FP 8-21 32171 Group User's Manual (Rev.2.00) 8 8.4 Port Peripheral Circuits INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits Figures 8.4.1 through 8.4.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. P00 - P07 (DB0-DB7) P10 - P17 (DB8-DB15) P20 - P27 (A23-A30) P30 - P37 (A15-A22) ___ ___ P41 (BLW / BLE) ___ ___ P42 (BHW / BHE) __ P43 (RD) ___ P44 (CS0) ___ P45 (CS1) P46 - P47 (A13-A14) P61 - P63 P225(A12) Direction register Data bus (DB0 - DB15) Port output latch Input function enable Note: * Although P00-07, P10-17, P20-27, P30-37, P41-47, and P225 serve as external bus interface control signal pins during external extension mode and processor mode, functional description is eliminated in this block diagram. Direction register P75 (RTDRXD) Data bus P77 (RTDCLK) (DB0 - DB15) P83 (RXD0) P86 (RXD1) P124 - P127 (TCLK0-TCLK3) P130 - P137 (TIN16-TIN23) P150, P153 (TIN0, TIN3) Peripheral P175 (RXD2) function input Port output latch Operation mode register Input function enable Notes: * :* denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. : * The input capacitance of each pin is approximately 10 pF. Figure 8.4.1 Port Peripheral Circuit Diagram (1) 8-22 32171 Group User's Manual (Rev.2.00) 8 ___ INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P64 (SBI) P221 / CRX Data bus (DB0 - DB15) SBI, CRX ____ P72 (HREQ) Data bus (DB0 - DB15) Direction register Port output latch Operation mode register HREQ Input function enable Notes: * :* denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. : * The input capacitance of each pin is approximately 10 pF. Figure 8.4.2 Port Peripheral Circuit Diagram (2) 8-23 32171 Group User's Manual (Rev.2.00) 8 ____ INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits P71 (WAIT) Direction register Data bus (DB0 - DB15) Port output latch Operation mode register WAIT Input function enable __ P70 (BCLK / WR) ____ P73 (HACK) P74 (RTDTXD) P76 (RTDACK) P82 (TXD0) P85 (TXD1) P93 - P97 (TO16-TO20) P100 - P107 (TO8-TO15) P110 - P117 (TO0-TO7) P174 (TXD2) P220 (CTX) Direction register Data bus (DB0 - DB15) Port output latch Operation mode register Peripheral function output Input function enable Notes: * :* denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. : * The input capacitance of each pin is approximately 10 pF. Figure 8.4.3 Port Peripheral Circuit Diagram (3) 8-24 32171 Group User's Manual (Rev.2.00) 8 P84 (SCLKI0, SCLKO0) P87 (SCLKI1, SCLKO1) INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Peripheral Circuits Direction register Data bus (DB0 - DB15) Port output latch Operation mode register UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input Input function enable MOD0 MOD1 MOD0 , MOD1 FP FP _____ RESET XIN JTRST RESET, XIN, JTRST JTDI JTCK JTMS JTDI, JTCK, JTMS JTDO JTDO OSC-VCC VCCI VCCE VDD Notes: * :* OSC-VCC, VCCI, VCCE, VDD denotes pins. indicates a parasitic diode. Make sure the voltages applied to each port do not exceed VCCE. Figure 8.4.4 Port Peripheral Circuit Diagram (4) 8-25 32171 Group User's Manual (Rev.2.00) 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Precautions on Input/output Ports 8.5 Precautions on Input/output Ports * When using the ports in output mode Because the Port Data Register values immediately after a reset are indeterminate, it is necessary that the initial value be written to the Port Data Register before setting the Port Direction Register for output. Conversely, if the Port Direction Register is set for output before writing to the Port Data Register, indeterminate values will be output for a while until the initial value is set in the Port Data Register. 8-26 32171 Group User's Manual (Rev.2.00) CHAPTER 9 DMAC 9.1 Outline of the DMAC 9.2 DMAC Related Registers 9.3 Functional Description of the DMAC 9.4 Precautions about the DMAC 9 9.1 Outline of the DMAC DMAC 9.1 Outline of the DMAC The 32171 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC Item Number of channel Transfer request Description 10 channels * Software trigger * Request from internal peripheral I/Os: A-D converter, multijunction timer, or serial I/O (reception completed, transmit buffer empty) * Transfer operation can be cascaded between DMA channels (Note) 256 times Maximum number of times transferred Transferable address space * 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF) * Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, between internal RAMs are supported 16 or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-address transfer Single transfer mode One of three modes can be selected for the source and destination: * Address fixed * Address incremental * Ring buffered Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 (Priority is fixed) Transfer data size Transfer method Transfer mode Direction of transfer Channel priority Maximum transfer rate 13.3 Mbytes per second (with 20 MHz internal peripheral clock) Interrupt request Transfer area Group interrupt request can be generated when each transfer count register underflows. 64 Kbytes from H'0080 0000 to H'0080 FFFF (Transferable in the entire internal RAM/SFR area) Note: * Transfer operation can be cascaded between DMA channels as shown below. Completion of one transfer in channel 0 starts DMA transfer in channel 1 Completion of one transfer in channel 1 starts DMA transfer in channel 2 Completion of one transfer in channel 2 starts DMA transfer in channel 0 Completion of one transfer in channel 3 starts DMA transfer in channel 4 Completion of one transfer in channel 5 starts DMA transfer in channel 6 Completion of one transfer in channel 6 starts DMA transfer in channel 7 Completion of one transfer in channel 7 starts DMA transfer in channel 5 Completion of one transfer in channel 8 starts DMA transfer in channel 9 Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer in channel 5 9-2 32171 Group User's Manual (Rev.2.00) 9 Software start One DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) DMA request selector Source address register Destination address register Transfer count register udf Internal bus DMAC 9.1 Outline of the DMAC DMA channel 0 DMA channel 1 Software start MJT (output event bus 0) One DMA0 transfer completed DMA channel 2 Software start MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel 3 Software start Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) DMA request selector Source Destination Transfer count udf DMA channel 4 Software start One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) DMA request selector Source Destination Transfer count udf Interrupt request DMA start Determination block Software start One DMA7 transfer completed All DMA0 transfers completed (udf) Serial I/O2 (reception completed) MJT (TIN20 input signal) DMA channel 5 DMA request selector Source Destination Transfer count udf Internal bus arbitration DMA channel 6 Software start Serial I/O1 (transmit buffer empty) One DMA5 transfer completed DMA channel 7 Software start Serial I/O2 (transmit buffer empty) One DMA6 transfer completed DMA channel 8 Software start MJT (input event bus 0) DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA request selector Source Destination Transfer count udf DMA channel 9 Software start One DMA8 transfer completed DMA request selector Source Destination Transfer count DMA start Determination block udf Interrupt request Internal bus arbitration Figure 9.1.1 Block Diagram of the DMAC 9-3 32171 Group User's Manual (Rev.2.00) 9 Clock bus Input event bus 3210 3210 DMAC 9.1 Outline of the DMAC Output event bus 0123 AD0 completed TIO8-udf S DMA0 udf end udf end udf end udf end DMAIRQ0 S DMA1 DMAIRQ0 TIN18 S DMA2 DMAIRQ0 TIN0 SIO0-TXD SIO1-RXD S DMA3 DMAIRQ0 SIO0-RXD TIN19 SIO2-RXD S DMA4 udf DMAIRQ0 TIN20 S DMA5 udf end udf end udf end DMAIRQ1 SIO1-TXD S DMA6 DMAIRQ1 SIO2-TXD S DMA7 DMAIRQ1 S DMA8 udf end udf DMAIRQ1 S DMA9 DMAIRQ1 3210 3210 0123 Figure 9.1.2 Causes of DMAC Requests Connection Diagram 9-4 32171 Group User's Manual (Rev.2.00) 9 9.2 DMAC Related Registers DMAC 9.2 DMAC Related Registers The diagram below shows a memory map of DMAC related registers. Address H'0080 0400 D0 +0 Address D7 D8 +1 Address DMA0-4 Interrupt Mask Register (DM04ITMK) D15 DMA0-4 Interrupt Request Status Register (DM04ITST) H'0080 0408 DMA5-9 Interrupt Request Status Register (DM59ITST) DMA5-9 Interrupt Mask Register (DM59ITMK) H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E DMA0 Channel Control Register (DM0CNT) DMA0 Transfer Count Register (DM0TCT) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA5 Channel Control Register (DM5CNT) DMA5 Transfer Count Register (DM5TCT) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA1 Channel Control Register (DM1CNT) DMA1 Transfer Count Register (DM1TCT) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA6 Channel Control Register (DM6CNT) DMA6 Transfer Count Register (DM6TCT) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA2 Channel Control Register (DM2CNT) DMA2 Transfer Count Register (DM2TCT) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA7 Channel Control Register (DM7CNT) DMA7 Transfer Count Register (DM7TCT) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) Blank addresses are reserved. Note: * The registers enclosed in thick frames can only be accessed in halfwords. Figure 9.2.1 DMAC Related Register Map (1/2) 9-5 32171 Group User's Manual (Rev.2.00) 9 Address H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 DMA9 Channel Control Register (DM9CNT) DMA4 Channel Control Register (DM4CNT) DMA8 Channel Control Register (DM8CNT) DMAC 9.2 DMAC Related Registers D0 +0 Address DMA3 Channel Control Register (DM3CNT) D7 D8 +1 Address DMA3 Transfer Count Register (DM3TCT) D15 DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA8 Transfer Count Register (DM8TCT) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA4 Transfer Count Register (DM4TCT) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA9 Transfer Count Register (DM9TCT) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478 DMA5 Software Request Generation Register (DM5SRI) DMA6 Software Request Generation Register (DM6SRI) DMA7 Software Request Generation Register (DM7SRI) DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI) Blank addresses are reserved. Note: * The registers enclosed in thick frames can only be accessed in halfwords. Figure 9.2.2 DMAC Related Register Map (2/2) 9-6 32171 Group User's Manual (Rev.2.00) 9 9.2.1 DMA Channel Control Register s DMA0 Channel Control Register (DM0CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL0 3 4 TENL0 5 TSZSL0 6 SADSL0 D7 DADSL0 MDSEL0 TREQF0 (Selects DMA0 source address direction) 1 : Incremental 7 DADSL0 (Selects DMA0 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-7 32171 Group User's Manual (Rev.2.00) 9 s DMA1 Channel Control Register (DM1CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL1 3 4 TENL1 5 TSZSL1 6 SADSL1 D7 DADSL1 MDSEL1 TREQF1 (Selects DMA1 source address direction) 1 : Incremental 7 DADSL1 (Selects DMA1 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-8 32171 Group User's Manual (Rev.2.00) 9 s DMA2 Channel Control Register (DM2CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL2 3 4 TENL2 5 TSZSL2 6 SADSL2 D7 DADSL2 MDSEL2 TREQF2 (Selects DMA2 source address direction) 1 : Incremental 7 DADSL2 (Selects DMA2 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-9 32171 Group User's Manual (Rev.2.00) 9 s DMA3 Channel Control Register (DM3CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL3 3 4 TENL3 5 TSZSL3 6 SADSL3 D7 DADSL3 MDSEL3 TREQF3 (Selects DMA3 source address direction) 1 : Incremental 7 DADSL3 (Selects DMA3 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-10 32171 Group User's Manual (Rev.2.00) 9 s DMA4 Channel Control Register (DM4CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL4 3 4 TENL4 5 TSZSL4 6 D7 MDSEL4 TREQF4 SADSL4 DADSL4 (Selects DMA4 source address direction) 1 : Incremental 7 DADSL4 (Selects DMA4 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-11 32171 Group User's Manual (Rev.2.00) 9 s DMA5 Channel Control Register (DM5CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL5 3 4 TENL5 5 TSZSL5 6 D7 MDSEL5 TREQF5 SADSL5 DADSL5 (Selects DMA5 source address direction) 1 : Incremental 7 DADSL5 (Selects DMA5 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-12 32171 Group User's Manual (Rev.2.00) 9 s DMA6 Channel Control Register (DM6CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL6 3 4 TENL6 5 TSZSL6 6 SADSL6 D7 DADSL6 MDSEL6 TREQF6 (Selects DMA6 source address direction) 1 : Incremental 7 DADSL6 (Selects DMA6 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-13 32171 Group User's Manual (Rev.2.00) 9 s DMA7 Channel Control Register (DM7CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL7 3 4 TENL7 5 TSZSL7 6 SADSL7 D7 DADSL7 MDSEL7 TREQF7 (Selects DMA7 source address direction) 1 : Incremental 7 DADSL7 (Selects DMA7 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-14 32171 Group User's Manual (Rev.2.00) 9 s DMA8 Channel Control Register (DM8CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL8 3 4 TENL8 5 TSZSL8 6 SADSL8 D7 DADSL8 MDSEL8 TREQF8 (Selects DMA8 source address direction) 1 : Incremental 7 DADSL8 (Selects DMA8 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-15 32171 Group User's Manual (Rev.2.00) 9 s DMA9 Channel Control Register (DM9CNT) DMAC 9.2 DMAC Related Registers D0 1 2 REQSL9 3 4 TENL9 5 TSZSL9 6 SADSL9 D7 DADSL9 MDSEL9 TREQF9 (Selects DMA9 source address direction) 1 : Incremental 7 DADSL9 (Selects DMA9 destination address direction) W= : Only writing a 0 is effective; when you write a 1, the previous value is retained. 0 : Fixed 1 : Incremental 9-16 32171 Group User's Manual (Rev.2.00) 9 DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel, set DMA transfer request flag, and the bits to select the cause of DMA request, enable DMA transfer, and set the transfer size and the source/destination address directions. (1) MDSELn (DMAn transfer mode select) bit (D0) This bit when in single transfer mode selects normal mode or ring buffer mode. Normal mode is selected by setting this bit to 0 or ring buffer mode is selected by setting it to 1. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode during which time transfer operation is continued until the transfer enable bit is reset to 0 (to disable transfer). No interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn transfer request flag) bit (D1) This flag is set to 1 when a DMA transfer request occurs. Reading this flag helps to know DMA transfer requests in each channel. The generated DMA request is cleared by writing a 0 to this bit. If you write a 1, the value you wrote is ignored and the bit retains its previous value. If a new DMA transfer request is generated for a channel whose DMA transfer request flag has already been set to 1, the next DMA transfer request is not accepted until the transfer under way in that channel is completed. (3) REQSLn (cause of DMAn request select) bits (D2, D3) These bits select the cause of DMA request in each DMA channel. (4) TENLn (DMAn transfer enable) bit (D4) Transfer is enabled by setting this bit to 1, so that the channel is ready for DMA transfer. Conversely, transfer is disabled by setting this bit to 0. However, if a transfer request has already been accepted, transfer in that channel is not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn transfer size select) bit (D5) This bit selects the number of bits to be transferred in one DMA transfer operation (unit of one transfer). The unit of one transfer is 16 bits when TSZSL = 0 or 8 bits when TSZSL = 1. (6) SADSLn (DMAn source address direction select) bit (D6) This bit selects the direction in which the source address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. (7) DADSLn (DAMn destination address direction select) bit (D7) This bit selects the direction in which the destination address changes as transfer proceeds. This mode can be selected from two choices: address fixed or address incremental. 9-17 32171 Group User's Manual (Rev.2.00) 9 9.2.2 DMA Software Request Generation Registers s DMA0 Software Request Generation Register (DM0SRI) s DMA1 Software Request Generation Register (DM1SRI) s DMA2 Software Request Generation Register (DM2SRI) s DMA3 Software Request Generation Register (DM3SRI) s DMA4 Software Request Generation Register (DM4SRI) s DMA5 Software Request Generation Register (DM5SRI) s DMA6 Software Request Generation Register (DM6SRI) s DMA7 Software Request Generation Register (DM7SRI) s DMA8 Software Request Generation Register (DM8SRI) s DMA9 Software Request Generation Register (DM9SRI) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0SRI - DM9SRI (Generates DMA software request) by writing any data Note: * This register can be accessed in either bytes or halfwords. The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when "Software start" has been selected for the cause of DMA request. DM0SRI - DM9SRI (DMA software request generate) bit A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when "Software" is selected as the cause of DMA transfer request (by setting the DMA Channel Control Register D2, D3 bits to "00"). 9-18 32171 Group User's Manual (Rev.2.00) 9 9.2.3 DMA Source Address Registers s DMA0 Source Address Register (DM0SA) s DMA1 Source Address Register (DM1SA) s DMA2 Source Address Register (DM2SA) s DMA3 Source Address Register (DM3SA) s DMA4 Source Address Register (DM4SA) s DMA5 Source Address Register (DM5SA) s DMA6 Source Address Register (DM6SA) s DMA7 Source Address Register (DM7SA) s DMA8 Source Address Register (DM8SA) s DMA9 Source Address Register (DM9SA) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0SA - DM9SA Note: * This register must always be accessed in halfwords. The DMA Source Address Register is used to set the source address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same source address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Source Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0SA-DM9SA (A16-A31 of the source address) By setting this register, specify the source address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the source address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the source address (with D0 corresponding to A16, and D15 corresponding to A31). 9-19 32171 Group User's Manual (Rev.2.00) 9 9.2.4 DMA Destination Address Registers s DMA0 Destination Address Register (DM0DA) s DMA1 Destination Address Register (DM1DA) s DMA2 Destination Address Register (DM2DA) s DMA3 Destination Address Register (DM3DA) s DMA4 Destination Address Register (DM4DA) s DMA5 Destination Address Register (DM5DA) s DMA6 Destination Address Register (DM6DA) s DMA7 Destination Address Register (DM7DA) s DMA8 Destination Address Register (DM8DA) s DMA9 Destination Address Register (DM9DA) D0 1 2 3 4 5 6 7 8 9 10 DMAC 9.2 DMAC Related Registers 11 12 13 14 D15 DM0DA - DM9DA Note: * This register must always be accessed in halfwords. The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that D0 corresponds to A16, and D15 corresponds to A31. Because access to this register is comprised of a current register, the value you get by reading this register is always the current value. When DMA transfer finishes (at which the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same destination address that was set in it before DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). Make sure the DMA Destination Address Register is always accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value read from this register is indeterminate. DM0DA-DM9DA (A16-A31 of the destination address) By setting this register, specify the destination address of DMA transfer in internal I/O space ranging from H'0080 0000 to H'0080 FFFF or in the RAM space. The 16 high-order bits of the destination address (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order bits of the destination address (with D0 corresponding to A16, and D15 corresponding to A31). 9-20 32171 Group User's Manual (Rev.2.00) 9 9.2.5 DMA Transfer Count Registers s DMA0 Transfer Count Register (DM0TCT) s DMA1 Transfer Count Register (DM1TCT) s DMA2 Transfer Count Register (DM2TCT) s DMA3 Transfer Count Register (DM3TCT) s DMA4 Transfer Count Register (DM4TCT) s DMA5 Transfer Count Register (DM5TCT) s DMA6 Transfer Count Register (DM6TCT) s DMA7 Transfer Count Register (DM7TCT) s DMA8 Transfer Count Register (DM8TCT) s DMA9 Transfer Count Register (DM9TCT) D8 9 10 11 12 13 DMAC 9.2 DMAC Related Registers 14 D15 DM0TCT - DM9TCT The DMA Transfer Count Register is used to set the number of times data is transferred in each channel. However, the value in this register is ignored during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the value you get by reading this register is always the current value. (However, if you read this register in a cycle immediately after transfer, the value you get is the value that was in the count register before the transfer began.) When transfer finishes, this count register underflows, so that the read value you get is H'FF. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers are completed (at which the transfer count register underflows), transfer in the cascaded channel starts. 9-21 32171 Group User's Manual (Rev.2.00) 9 9.2.6 DMA Interrupt Request Status Registers s DMA0-4 Interrupt Request Status Register (DM04ITST) DMAC 9.2 DMAC Related Registers D0 1 2 3 4 5 6 D7 DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 The DMA0-4 Interrupt Request Status Register lets you know the status of interrupt requests in channels 0-4. If the DMAn interrupt request status bit (n = 0 to 4) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 0 to 4) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: * The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "IREQ bit" of the DMA Interrupt Control Register(IDMA04CR) that the interrupt controller has. When writing to the DMA0-4 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. 9-22 32171 Group User's Manual (Rev.2.00) 9 s DMA5-9 Interrupt Request Status Register (DM59ITST) DMAC 9.2 DMAC Related Registers D0 1 2 3 4 5 6 D7 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 The DMA5-9 Interrupt Request Status Register lets you know the status of interrupt requests in channels 5-9. If the DMAn interrupt request status bit (n = 5 to 9) is set to 1, it means that a DMAn interrupt request in the corresponding channel has been generated. DMITSTn (DMAn interrupt request status) bit (n = 5 to 9) [Setting the DMAn interrupt request status bit] This bit can only be set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing a 0 in software. Note: * The DMAn interrupt request status bit cannot be cleared by writing a 0 to the "IREQ bit" of the DMA Interrupt Control Register(IDMA59CR) that the interrupt controller has. When writing to the DMA5-9 Interrupt Request Status Register, be sure to set the bits you want to clear to 0 and all other bits to 1. The bits which are thus set to 1 are unaffected by writing in software, and retain the value they had before you wrote. 9-23 32171 Group User's Manual (Rev.2.00) 9 9.2.7 DMA Interrupt Mask Registers s DMA0-4 Interrupt Mask Register (DM04ITMK) DMAC 9.2 DMAC Related Registers D8 9 10 11 12 13 14 D15 DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 The DMA0-4 Interrupt Mask Register is used to mask interrupt requests in DMA channels 0-4. DMITMKn (DMAn interrupt request mask) bit (n = 0 to 4) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register. 9-24 32171 Group User's Manual (Rev.2.00) 9 s DMA5-9 Interrupt Mask Register (DM59ITMK) DMAC 9.2 DMAC Related Registers D8 9 10 11 12 13 14 D15 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 The DMA5-9 Interrupt Mask Register is used to mask interrupt requests in DMA channels 5-9. DMITMKn (DMAn interrupt request mask) bit (n = 5 to 9) DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1. However, when an interrupt request is generated, the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register. 9-25 32171 Group User's Manual (Rev.2.00) 9 DM04ITST DMAC 9.2 DMAC Related Registers 5-source inputs DMA transfer interrupt 0 (Level) DMA3UDF b4 b12 DMITST3 F/F DMITMK3 F/F DMA2UDF b5 b13 DMITST2 F/F DMITMK2 F/F DMA1UDF b6 b14 DMITST1 F/F DMITMK1 F/F DMA0UDF b7 b15 DMITST0 F/F DMITMK0 F/F Figure 9.2.3 Block Diagram of DMA Transfer Interrupt 0 9-26 32171 Group User's Manual (Rev.2.00) 9 DM59ITST DMAC 9.2 DMAC Related Registers 5-source inputs DMA transfer interrupt 1 (Level) DMA8UDF b4 b12 DMITST8 F/F DMITMK8 F/F DMA7UDF b5 b13 DMITST7 F/F DMITMK7 F/F DMA6UDF b6 b14 DMITST6 F/F DMITMK6 F/F DMA5UDF b7 b15 DMITST5 F/F DMITMK5 F/F Figure 9.2.4 Block Diagram of DMA Transfer Interrupt 1 9-27 32171 Group User's Manual (Rev.2.00) 9 9.3 Functional Description of the DMAC 9.3.1 Cause of DMA Request DMAC 9.3 Functional Description of the DMAC For each DMA channel (channels 0 to 9), DMA transfer can be requested from multiple sources. There are various causes of DMA transfer, so that DMA transfer can be started by a request from internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers in a DMA channel (cascade mode). The cause of DMA request is selected using the cause of request select bit provided for each channel, REQSLn (DMAn Channel Control Register bits D2, D3). The table below lists the causes of DMA requests in each channel. Table 9.3.1 Causes of DMA Requests in DMA0 and Generation Timings REQSL0 0 0 Cause of DMA Request Software start or one DMA2 transfer completed DMA Request Generation Timing When any data is written to DMA0 Software Request Generation Register (software start) or one DMA2 transfer is completed (cascade mode) 0 1 1 1 0 1 A-D0 conversion completed MJT (TIO8_udf) MJT (input event bus 2) When A-D0 conversion is completed When MJT TIO8 underflow occurs When MJT's input event bus 2 signal is generated Table 9.3.2 Causes of DMA Requests in DMA1 and Generation Timings REQSL1 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA1 Software Request Generation Register 0 1 1 1 0 1 MJT (output event bus 0) None (Use inhibited) One DMA0 transfer completed When MJT's output event bus 0 signal is generated - When one DMA0 transfer is completed (cascade mode) 9-28 32171 Group User's Manual (Rev.2.00) 9 REQSL2 0 0 Cause of DMA Request Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.3 Causes of DMA Requests in DMA2 and Generation Timings DMA Request Generation Timing When any data is written to DMA2 Software Request Generation Register 0 1 1 1 0 1 MJT (output event bus 1) MJT (TIN18 input signal) One DMA1 transfer completed When MJT's output event bus 1 signal is generated When MJT's TIN18 input signal is generated When one DMA1 transfer is completed (cascade mode) Table 9.3.4 Causes of DMA Requests in DMA3 and Generation Timings REQSL3 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA3 Software Request Generation Register 0 1 1 1 0 1 Serial I/O0 (transmit buffer empty) Serial I/O1 (reception completed) MJT (TIN0 input signal) When serial I/O0 transmit buffer is emptied When serial I/O1 reception is completed When MJT's TIN0 input signal is generated Table 9.3.5 Causes of DMA Requests in DMA4 and Generation Timings REQSL4 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA4 Software Request Generation Register 0 1 1 1 0 1 One DMA3 transfer completed Serial I/O0 (reception completed) MJT (TIN19 input signal) When one DMA3 transfer is completed (cascade mode) When serial I/O0 reception is completed When MJT's TIN19 input signal is generated 9-29 32171 Group User's Manual (Rev.2.00) 9 REQSL5 0 0 Cause of DMA Request Software start or one DMA7 transfer completed DMAC 9.3 Functional Description of the DMAC Table 9.3.6 Causes of DMA Requests in DMA5 and Generation Timings DMA Request Generation Timing When any data is written to DMA5 Software Request Generation Register or one DMA7 transfer is completed (cascade mode) 0 1 1 1 0 1 All DMA0 transfers completed Serial I/O2 (reception completed) MJT (TIN20 input signal) When all DMA0 transfers are completed (cascade mode) When serial I/O2 reception is completed When MJT's TIN20 input signal is generated Table 9.3.7 Causes of DMA Requests in DMA6 and Generation Timings REQSL6 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA6 Software Request Generation Register 0 1 1 1 0 1 Serial I/O1 (transmit buffer empty) None (Use inhibited) One DMA5 transfer completed When serial I/O1 transmit buffer is emptied - When one DMA5 transfer is completed (cascade mode) Table 9.3.8 Causes of DMA Requests in DMA7 and Generation Timings REQSL7 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA7 Software Request Generation Register 0 1 1 1 0 1 Serial I/O2 (transmit buffer empty) None (Use inhibited) One DMA6 transfer completed When serial I/O2 transmit buffer is emptied - When one DMA6 transfer is completed (cascade mode) 9-30 32171 Group User's Manual (Rev.2.00) 9 REQSL8 0 0 Cause of DMA Request Software start DMAC 9.3 Functional Description of the DMAC Table 9.3.9 Causes of DMA Requests in DMA8 and Generation Timings DMA Request Generation Timing When any data is written to DMA8 Software Request Generation Register 0 1 1 1 0 1 MJT (input event bus 0) None (Use inhibited) None (Use inhibited) When MJT's input event bus 0 signal is generated - - Table 9.3.10 Causes of DMA Requests in DMA9 and Generation Timings REQSL9 0 0 Cause of DMA Request Software start DMA Request Generation Timing When any data is written to DMA9 Software Request Generation Register 0 1 1 1 0 1 None (Use inhibited) None (Use inhibited) One DMA8 transfer completed - - When one DMA8 transfer is completed (cascade mode) 9-31 32171 Group User's Manual (Rev.2.00) 9 9.3.2 DMA Transfer Processing Procedure DMAC 9.3 Functional Description of the DMAC Shown below is an example of how to control DMA transfer in cases when performing transfer in DMA channel 0. DMA transfer processing starts Setting interrupt controller related registers Set the interrupt controller's DMA0-4 Interrupt Control Register * Interrupt priority level Set DMA0 Channel Control Register * Transfers disabled Set DMA0-4 Interrupt Request Status Register * Clears interrupt request status bit * Enables interrupt request Set DMA0-4 Interrupt Mask Register Setting DMAC related registers Set DMA0 Source Address Register * Source address of transfer Set DMA0 Destination Address Register * Destination address of transfer Set DMA0 Count Register * Number of times DMA transfer performed * Transfer mode, cause of request, transfer size, address direction, and transfer enable Set DMA0 Channel Control Register Starting DMA transfer DMA transfer starts as requested by internal peripheral I/O Transfer count register underflows DMA transfer completed Interrupt request generated DMA operation completed Figure 9.3.1 Example of a DMA Transfer Processing Procedure 9-32 32171 Group User's Manual (Rev.2.00) 9 9.3.3 Starting DMA DMAC 9.3 Functional Description of the DMAC Use the REQSL (cause of DMA request select) bit to set the cause of DMA request. To enable DMA, set the TENL (DMA transfer enable) bit to 1. DMA transfer begins when the specified cause of DMA request becomes effective after setting the TENL (DMA transfer enable) bit to 1. 9.3.4 Channel Priority Channel 0 has the highest priority. The priority of this and other channels is shown below. Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 This order of priority is fixed and cannot be changed. Among channels for which DMA transfers are requested, the channel that has the highest priority is selected. Channel selection is made every transfer cycle (one DMA bus cycle consisting of three machine cycles). 9.3.5 Gaining and Releasing Control of the Internal Bus For any channel, control of the internal bus is gained and released in "single transfer DMA" mode. In single transfer DMA, the DMA gains control of the internal bus when DMA transfer request is accepted and after executing one DMA transfer (consisting of one read cycle + one write cycle of internal peripheral clock), returns bus control to the CPU. The diagram below shows DMA operation in single transfer DMA. Requested Internal bus arbitration (control requested by DMAC) Gained Requested Gained Requested Gained CPU Internal bus DMAC R W Released Released Released R W R W One DMA transfer One DMA transfer R: Read W: Write One DMA transfer Figure 9.3.2 Gaining and Releasing Control of the Internal Bus 9-33 32171 Group User's Manual (Rev.2.00) 9 9.3.6 Transfer Units DMAC 9.3 Functional Description of the DMAC Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 256 times. The value of the DMA Transfer Count Register is decremented by one each time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored. 9.3.8 Address Space The address space in which data can be transferred by DMA is the internal peripheral I/O or 64 Kbytes of RAM space (H'0080 0000 through H'0080 FFFF) for either source or destination. To set the source and destination addresses in each channel, use the DMA Source Address Register and DMA Destination Address Register. 9.3.9 Transfer Operation (1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is temporarily taken into the DMA's internal temporary register.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, the same applies to both bus protocol and bus timing as in peripheral module access from the CPU. (3) Transfer rate The maximum transfer rate is calculated using the equation below: 1 1 / f (BCLK) x 3 cycles Maximum transfer rate [bytes/second] = 2 bytes x 9-34 32171 Group User's Manual (Rev.2.00) 9 (4) Address count direction and address changes DMAC 9.3 Functional Description of the DMAC The direction in which the source and destination addresses are counted as transfer proceeds ("Address fixed" or "Address incremental") is set for each channel using the SADSL (source address direction select) and DADSL (destination address select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes Address Count Direction Address fixed Transfer Unit 8 bits 16 bits Address incremental 8 bits 16 bits Address Change for One DMA 0 0 +1 +2 (5) Transfer count value The transfer count value is decremented by one at a time irrespective of the size of transfer unit (8 or 16 bits). 9-35 32171 Group User's Manual (Rev.2.00) 9 (6) Transfer byte positions DMAC 9.3 Functional Description of the DMAC When the transfer unit = 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address, or from odd address to even address.) When the transfer unit = 16 bits, the LSB of the address register (D15 of the address register) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid transfer byte positions. +0 D0 D7 D8 8 bits 8 bits +1 D15 +0 D0 D7 D8 16 bits +1 D15 Source Destination 8 bits 8 bits 16 bits Figure 9.3.3 Transfer Byte Positions 9-36 32171 Group User's Manual (Rev.2.00) 9 (7) Ring buffer mode DMAC 9.3 Functional Description of the DMAC When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B'00000. The address increment operation in ring buffer mode is described below. When the transfer unit = 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B'11111, they are recycled to B'00000 by the next increment operation, thus returning to the start address again. When the transfer unit = 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B'111110, they are recycled to B'000000 by the next increment operation, thus returning to the start address again. When the source address has been set to be incremented, it is the source address that recycles to the start address; when the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially being B'00000. During ring buffer mode, the transfer count register is ignored. Also, once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to (to disable transfer). Figure 9.3.4 Example of Address Increment Operation in 32-Channel Ring Buffer Mode 9-37 32171 Group User's Manual (Rev.2.00) 9 9.3.10 End of DMA and Interrupt DMAC 9.3 Functional Description of the DMAC In normal mode, DMA transfer is terminated when the transfer count register underflows. When transfer finishes, the transfer enable bit is cleared to 0 and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, this interrupt is not generated for channels where interrupt requests have been masked by the DMA Interrupt Mask Register. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to 0 (to disable transfer). In this case, therefore, the DMA transfer-completed interrupt request is not generated. Nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 Status of Each Register after Completion of DMA Transfer When DMA transfer is completed, the status of the source address and destination address registers becomes as follows: (1) Address fixed * The value set in the address register before DMA transfer started remains intact (fixed). (2) Address incremental * For 8-bit transfer, the value of the address register is the last transfer address + 1. * For 16-bit transfer, the value of the address register is the last transfer address + 2. The transfer count register when DMA transfer completed is in an underflow state (H'FF). Therefore, to perform another DMA transfer, set the transfer count register newly again, except when you are performing transfers 256 times (H'FF). 9-38 32171 Group User's Manual (Rev.2.00) 9 9.4 Precautions about the DMAC * About writing to DMAC related registers DMAC 9.4 Precautions about the DMAC Because DMA transfer involves exchanging data via the internal bus, basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled (transfer enable bit = 0). When transfer is enabled, do not write to the DMAC related registers because write operation to those registers, except the DMA transfer enable bit, transfer request flag, and the DMA Transfer Count Register which is protected in hardware, is instable. The table below shows the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status When transfer is enabled When transfer is disabled : Can be accessed ; : Cannot be accessed Transfer enable bit Transfer request flag Other DMAC related registers For even registers that can exceptionally be written to while transfer is enabled, the following requirements must be met. DMA Channel Control Register's transfer enable bit and transfer request flag For all other bits of the channel control register, be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag. Note that you only can write a 0 to the transfer request flag as valid data. DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data you write to this register is ignored. Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer In this case, you are writing to the DMAC related registers while DMA is enabled, but this practically does not present any problem. However, you cannot DMA-transfer to the DMAC related registers on the local channel itself in which you are currently operating. 9-39 32171 Group User's Manual (Rev.2.00) 9 DMAC 9.4 Precautions about the DMAC * Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers' initial values by DMA transfer), do not write to the DMAC related registers on the local channel itself through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) Only if residing on other channels, you can write to the DMAC related registers by means of DMA transfer. (For example, you can rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0.) * About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write 1s to all bits but the one you want to clear. The bits to which you wrote 1s retain the previous data they had before the write. * About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the DMA Channel Control Register's transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, you can rewrite the DMA Source Address and DMA Destination Address Registers by DMA transfer from one channel to another. 9-40 32171 Group User's Manual (Rev.2.00) CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.2 Common Units of Multijunction Timer 10.3 TOP (Output-related 16-bit Timer) 10.4 TIO (Input/Output-related 16-bit Timer) 10.5 TMS (Input-related 16-bit Timer) 10.6 TML (Input-related 32-bit Timer) 10 10.1 Outline of Multijunction Timers MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event bus at multiple points that they are called the "multijunction" timers. The 32171 has four types of multijunction timers as listed in the table below, providing a total of 37 channels of timers. Table 10.1.1 Outline of Multijunction Timers Name TOP (Timer Output) Type Output-related 16-bit timer (down-counter) Number of Channels Description 11 One of three output modes can be selected by software. |